SU1647864A1 - Single pulse driver - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is to increase the noise immunity by completely eliminating the false alarms of the device from single emissions of any polarity that do not coincide with the leading edge of the sync pulse, is achieved by introducing RS-trigger-Fepa 5. The device also contains RS-triggers 1-4, AND-HE elements 6 -9, inverter 10, input bus 11. 12-clock bus, output bus 13. 2 Il.

Description

The invention relates to a pulse technique and can be used in automation devices and computer technology.

The purpose of the invention is to increase noise immunity by completely eliminating false alarms of the device from single emissions of any polarity that do not coincide with the leading edge of the clock.

Figure 1 shows the electrical functional diagram of the device; figure 2 timing diagrams explaining his work.

A device for generating a single pulse contains from the first to the fifth RS-flip-flops 1-5, from the first to the fourth elements of NAND 6-9, an inverter 10.

The first input of the first AND-NOT 6 element is connected to the direct output of the first RS trigger 1, the R-input of which is connected to the output of the second AND-NOT 7 element, the first input of which is connected to the input bus 11 through the inverter 10, the R-input of the second RS trigger 2 is connected to the output of the third element AND-NOT 8, the R-input of the third RS-trigger is connected to the direct output of the RS-trigger, the S-input is connected to the first input of the fourth element AND-NOT 9, the inverse output of the fifth RS-trigger 5 is connected to an additional R-input the first RS-trigger 1, the S-input of which is connected to the first input of the third element AND-NOT 8 and p the first input of the second AND-NOT 7 element, the second input of which is connected to the inverse output of the third RS trigger 3, the S-input of which is connected to the bus 12 of the clock pulses, with the R-input of the fourth RS-trigger 4 and the third input of the second AND-NOT 7 element. direct output - with the S-input of the second RS-flip-flop 2 and the second input of the first AND-NOT 6 element, the output of which is connected to the S-input of the fourth RS-flip-flop 4 and with the second input of the fourth AND-NOT 9 element, the output of which is connected to the second the input of the third element AND NOT 8, and the third input of the first element AND NOT 6 connected to th output of the fifth flip-flop RS-5, S-input coupled to a direct output of the first RS-triggera'1, R-input - with the inverted output of the fourth RS-flip-flop 4 and an output bus

thirteen.

The device operates as follows.

Let at the initial moment before applying the first pulse to bus 12 (Fig.2A) on bus 11 (Fig.2b) there is a positive (single) potential, at the inverse output of trigger 5 (Fig.2z) and the direct output of trigger 2 (Fig.2l) ) there is also a single potential. The zero potential on bus 12 provides the formation of single signals at the direct output of trigger 3 (Fig.2c), the inverse output of trigger 4 (Fig.2e) and at the output of element 9 (Fig.2p). The zero signal at the output of inverter 10 (FIG. 2T) provides the appearance of single signals at the direct output of trigger 1, at the outputs of elements 7 and 8. At the R-input of trigger 3, R-inputs of trigger 1 and trigger 2, at the S-input of trigger 5 single signals appear, which leads to the formation of zero signals at their outputs. The zero signal at the direct output of trigger 5 determines the formation of a single signal at the output of element 6. This signal is fed to the S-input of trigger 4 (Fig.2d), which ensures that a zero signal appears at its direct output.

Thus, all output signals of the device are initially determined.

At the time to the beginning of the pulse on the bus 12 (Fig.2A) at both inputs of the element 9 (Fig.2p) are single signals, and a zero signal is generated at its output. The remaining signals at the outputs of the logic elements at the time to remain unchanged,

At the time of the appearance of a zero signal on the bus 11, at the output of the inverter 10 (Fig.2, t) a single signal appears. The remaining signals at the outputs of the logic elements at the moment ΐτ remain unchanged.

When an interference occurs at a time between ti and t2, the interference signal appears only at the output of the inverter 10, there is no other reaction of the device to the interference, the output signal of the device does not change.

At the moment t2 of the end of the pulse on the bus 12 at the output of element 9 appears a single signal. This signal is fed to the input of element 8, at the other input of which there is also a single signal. This determines the formation of a zero signal at the output of element 8 (Fig.2n). This zero signal switches trigger 2, while a single signal is generated at the inverse output of trigger 2 (Fig.2m), and zero at the direct output of trigger 2 (Fig.2m). which in turn generates a single signal at the inverse output of trigger 3 (Fig.2g). The remaining signals at the outputs of the logic elements at time t2 remain unchanged.

When interference occurs at a time between t2 and t3, the interference signal appears at the output of the inverter 10 and at the output of the element 8 in the form of a single short signal. After the cessation of interference, the signals at the outputs of these elements return to their original state. The output signal of the device does not change.

At the moment t3 of the beginning of the pulse, on the bus 12 at the S-input of trigger 2 (Fig.2c), single signals appear at the inputs of elements 9 and 7 (Fig.2p, p), which leads to the formation of zero signals at the outputs of these elements. A zero signal at the direct output of trigger 3 confirms a single signal at the output of element 6 (Fig.2c) and switches trigger 2, while a single signal appears at the direct output of trigger 2 (Fig.2l), at the inverse output of trigger 4 (Fig.2m) - zero. The zero signal at the output of element 9 (Fig.2p) generates a single signal at the output of element 8. The zero signal at the output of element 7 (Fig.2p) switches trigger 1, while a single signal appears at the inverse output of trigger 1 (Fig.2k), and at the direct output of trigger 1 (Fig.2i) - zero, which, in turn, confirms a single signal at the output of element 6 (Fig.2c) and switches trigger 5. With this switching on the direct output of trigger 5 (Fig.2zh) a single signal appears, and on the inverse output of trigger 5 (Fig.2z) - zero. The remaining signals at the outputs of the logic elements at time t3 remain unchanged.

When exposed to interference at a time between ΐ3 and xa, an interference signal appears at the output of the inverter 10 and at the direct output of the trigger 1 (Fig.2i) and at the output of the element 7 (Fig.2p). Trigger 1 does not switch, since one of the R inputs of trigger 1 (Fig.2k) has a zero signal (from the inverse output of trigger 5). After the cessation of interference, the signals at the outputs of these elements return to their original state. The output signal of the device does not change.

At the time and end of the pulse on the bus 12 on the direct output of the trigger 3 (Fig.2, c) and the outputs of the elements 9 and 7 (Fig.2p and p) appear single signals. A single signal from the output of element 9 is fed to the input of element 8, while at the both inputs of the latter there are single signals, and the output is a zero signal, which, in turn, switches trigger 2, while a single signal appears at its inverse output, and on its direct output is zero. It should be noted that a short negative (zero) impulse appears on the inverted output of trigger 3, which is caused by a return to the initial state after switching trigger 2 (from a zero signal at the direct output of trigger 2). This short pulse does not affect the output signal of the device (Fig. 2f). The remaining signals at the outputs of the logic elements at time t4 remain unchanged.

When interference occurs at a time between U and ts, the interference signal appears at the output of inverter 10. At the direct output of trigger 1 and at the input of element 2 as a short single signal. The interference signal at the direct output of trigger 1 leads to the appearance of interference at the output of element 6 in the form of a short zero signal, which, in turn, leads to the short-term appearance of a single signal at the direct output of trigger 4 (Fig.2d). In this case, trigger 4 does not switch, since there is a zero signal from bus 12 at its R-input. After the cessation of interference, the signals at the outputs of all these elements return to their original state. The output signal of the device does not change.

At the moment ts of the beginning of the pulse on bus 12 at the S-output of trigger 3, single signals appear at the inputs of elements 9 and 7, which leads to the formation of zero signals at the outputs of these elements. The zero signal at the output of element 9 determines the formation of a single signal at the output of element 8. A zero signal at the direct output of trigger 3 switches trigger 2, while a single signal appears at its direct output and zero at its inverse output. The remaining signals at the outputs of the logic elements at time ts remain unchanged.

At the time t6 when the zero pulse ends, on the bus 11 at the output of the inverter 10 a zero signal appears, which generates single signals at the direct output of the trigger 1 and at the output of the element 7 and confirms the single signal at the output of the element 8. The remaining signals at the outputs of the logic elements at the time t6 remain unchanged .

When interference occurs at a time between t6 and t7, the interference signal appears at the output of inverter 10 as a short single signal and at the direct output of trigger 1 and the output of element 7 as a short zero signal. In this case, trigger 1 does not switch, since there is a zero signal on the inverse output of trigger 5 at its R input. After the cessation of interference, the signals at the direct output of trigger 1 and the output of element 7 and inverter 10 are returned to their original state / The device output signal does not change.

At the time t7 of the end of the pulse on the bus 12 on the direct output of the trigger 3 and the output of the element 9 appear single signals.

At the same time, at the R-input of trigger 3 and the inputs of element 6, single signals appear, which determines the formation of zero signals at their outputs. The zero signal at the inverted output of trigger 3 leads to the appearance of a single signal at the direct output of trigger 4. The remaining signals at the outputs of the logic elements at time t7 remain unchanged.

When interference occurs at an instant between t7 and t8, the interference signal appears at the output of inverter 10 and at the output of element 8 in the form of a short zero pulse. This short pulse triggers trigger 2 with its leading edge, while a single signal appears on its inverse output, and a zero signal appears on its direct output, which, in turn, determines the formation of a single signal on the inverse output of trigger 3. After the interference is stopped, the signals on the inverter 10 and element 8 are returned to their original state. Trigger 2 and element 8 do not return to their original state after exposure to interference, but this does not affect the output signal, which remains unchanged.

. At the moment ΐβ of the beginning of the pulse on bus 12 at the R-input of trigger 3, the R-input of trigger 4 and at the inputs of element 9, single signals appear, which determines the appearance of zero signals at their outputs. The signal at the inverse output of trigger 3 is the output and appears after the end of the pulse on bus 11 with the arrival of the next pulse on bus 12 at the required time. Interference does not affect him in any way.

A zero signal at the direct output of trigger 3 leads to the appearance of a single signal at the output of element 6 and switches trigger 2, while a single signal appears at its direct output, and zero at its inverse. A zero signal at the inverted output of trigger 4 switches trigger 5, while a single signal appears at its inverse output, and zero at its direct output. On the R-inputs of trigger 1, single signals appear, which leads to the formation of a zero signal at its inverse output. The remaining signals at the outputs of the logic elements at time t8 remain unchanged.

When an interference occurs at a time between tents, an interference signal appears at the output of the inverter 10 and at the output of the element 7 in the form of a short zero pulse. This pulse switches trigger 1, while a single signal appears on the inverse output of trigger 1, and a zero signal appears on the direct output of trigger 1, which leads to the formation of a single signal on the direct output of the trigger. After the cessation of interference, the signals at the outputs of all these elements return to their original state, including trigger 1. The interference signal has no effect on the output signal and the formation of a single output pulse at the inverse output of trigger 1 continues during this period of time.

At the moment t9 of the end of the pulse, the trigger 3 is switched on the bus 12, at the same time a single signal appears on the direct output, and zero on its inverse output, and the output pulse formation on the inverse output of the trigger 4 ends, where a single signal appears. It should be noted that the reaction of the influence of interference that passed at the time between t7 and te at the inverse output of trigger 3 stops. The remaining signals at the outputs of the logic elements at time tg remain unchanged.

Consider the appearance of noise at a point in time between tg and tio. those. after the formation of a single pulse at the output of the device. This point is the most dangerous for other known schemes, including the prototype scheme. When an interference occurs, the interference signal appears at the output of the inverter 10 and at the output of the element 8 in the form of a short zero pulse that switches trigger 2, while a single signal appears at its inverse output, and a zero signal at its direct output, which, in turn, generates a single signal at the inverted output of trigger 3. After the cessation of interference, the output signals at inverter 10 and element 8 are returned to their original state. Trigger 1 remains in the switched state and a single signal remains at the inverse output of trigger 3. However, this does not affect the output signal, which remains unchanged.

At the moment tio of the beginning of the pulse, on the S-input of trigger 3 and the inputs of element 9, the unit signals appear on the bus 12, which ensures the formation of zero signals at the direct output of trigger 3 and the output of element 9. A zero signal at the direct output of trigger 3 switches trigger 2, thereby removing the reaction from the effects of interference on this trigger. In this case, a single signal appears at the direct output of trigger 2, and zero at its inverse output. The remaining signals at the outputs of the logic elements at the time tio remain unchanged.

At the moment ti 1 of the end of the pulse on the bus 12 at the outputs of the trigger 3 and element 9 appear single signals. In this case, single signals appear at the R-input of trigger 3, which ensures the formation of a zero signal at its inverse output, and thereby the reaction from the effect of interference in the time interval between tg and tio is removed. The remaining signals at the outputs of the logic elements at time tn remain unchanged.

At the time of the start of the negative signal on the bus 12 at the output of the inverter 10, a single signal appears. In this case, single signals appear at both inputs of element 8, which leads to the formation of a zero signal at its output, which switches trigger 2, while a single signal appears at the inverted output of trigger 2, and a zero signal at its direct output, which, in turn, , leads to the appearance of a single signal at the inverse output of the trigger 3 '. The remaining signals at the outputs of the logic elements at the time ti2 remain unchanged.

When interference occurs at a point in time between P2 and PZ, an interference signal appears at the output of the inverter 10 and at the output of element 8. After the termination of the interference, the signals at the outputs of these elements return to their original state. The output signal of the device remains unchanged.

At the moment ti3 of the beginning of the pulse, on the S-input of trigger 3 and all inputs of elements 7 and 9 there are single signals at the S-input, which leads to the formation of zero signals on the inverse output of trigger 3 and outputs of elements 7 and 9. A zero signal at the output of element 9 leads to the appearance of a single signal at the output of element 8. A zero signal at the direct output of trigger 3 switches trigger 2, while a single signal is at the direct output of trigger 2, and zero at its inverse output. The zero signal at the output of element 7 switches trigger 1, while on its inverse output there is a single signal, and at its direct output a zero signal that confirms a single signal at the output of element 6 and switches trigger 5, while a single signal appears at its direct output , and on its inverse output - zero. The remaining signals at the outputs of the logic elements at time ti3 remain unchanged.

When interference occurs at a time between ti3 and tn, the interference signal appears at the output of the inverter 10 and at the direct and inverse outputs of trigger 1. After the termination of the interference, the signals at the outputs of this trigger return to their original state. The output signal of the device remains unchanged.

At the moment tn of the end of the pulse on the bus 12 on the direct output of the trigger 3 and at the inputs of the element 9 appear single signals. At both inputs of element 8, single signals appear, which determines the appearance of a zero signal at its output. This zero signal switches trigger 2, while a single signal appears on its inverse output, and a zero signal appears on its direct output. It should be noted that at the inverted output of trigger 3, a short negative pulse appears, caused by the operation of this element. This short pulse does not affect the output signal of the device. The remaining signals at the outputs of the logic elements at time ti4 remain unchanged.

At the time tis the end of the negative pulse on the bus 11 at the direct output of the trigger 1 and the outputs of the elements 7 and 8, single signals are formed. Moreover, at the inputs of element 6 there are single signals, which leads to the formation of a zero signal at its output, which, getting to the R-input of trigger 4, forms a single signal at its direct output. The remaining signals at the outputs of the logic elements at time ti5 remain unchanged.

When an interference occurs at a time between ti5 and not, an interference signal appears on the inverter 10 and the S-input of trigger 1 and element 8 in the form of zero short pulses. A zero short pulse at the direct output of trigger 1 leads to the appearance of a single pulse at the output of element 6. At the same time, single signals appear at the S-input of trigger 4, and a short negative pulse is formed at its direct output. After the cessation of interference, the signals at the outputs of all these elements return to their original state. The output signal of the device remains unchanged.

At the moment ti6 of the beginning of the pulse, on the S- and R-inputs of triggers 3 and 4 there are single signals, which leads to the appearance of zero signals on the direct output of trigger 3 and on the inverse output of trigger 4, and the signal from the inverse output of trigger 4 is the output . A zero signal at the direct output of trigger 3 leads to the formation of a single signal at the output of element 6 and switches trigger 2, while a single signal appears at its direct output and zero at its inverse output. After the appearance of a single signal at the output of element 6, single inputs appear at both inputs of element 9, which determines the appearance of a zero signal at its output, which confirms a single signal at the output of element 8. A zero signal at the inverse output of trigger 4 switches trigger 5, while a single signal appears in the inverted output, and zero at its direct output. In this case, single signals appear at the R-inputs of trigger 1, which leads to the formation of a zero signal at its inverse output. This signal confirms a single signal at the direct output of trigger 1. The remaining signals at the outputs of the logic elements remain unchanged.

At the moment tn of the end of the pulse, a single signal is generated at the output of element 9 and triggers 3 and 4 are switched; at the same time, single potentials appear on the direct and inverse outputs of triggers 3 and 4, and zero on the inverse output of trigger 3 and the direct output of trigger 4 ~ .

A zero signal at the inverse output of trigger 3 confirms a single signal at the output of element 7, and a zero signal at the direct output of trigger 4 confirms a single signal at the inverse output of trigger 4. The remaining signals at the outputs of the logic elements at time t p remain unchanged.

At the moment of the beginning of the impulse tie, on the bus 12, single signals appear at all inputs of element 9, which leads to the appearance of a zero signal at its output. The remaining signals at the outputs of the logic elements at the time of tie remain unchanged.

When interference occurs at a time between tie and 119, the interference signal appears only at the output of the inverter 10. After the termination of the interference, the inverter returns to its original state. The output signal of the device remains unchanged.

At the moment 119 of the end of the pulse on the bus 12 at the output of the element 9 appears a single signal. The remaining signals at the outputs of the logic elements at the time tw remain unchanged.

In the process of describing the operation of the circuit, all possible cases of the appearance of interference on the control bus 12 were considered: In this case, in no case of malfunction of the device was observed.

Claims (1)

Claim A device for generating a single pulse, containing the first RS trigger, the direct output of which is connected to the first input of the first element AND-NOT. R input with the output of the second AND-NOT element, the first input of which is connected to the inverter output, the R-input of the second RS-trigger is connected to the output of the third AND-NOT element, the S-input of the third RS-trigger is connected to the first input of the fourth AND-NOT element, the fourth RS-trigger, the input bus, the clock bus and the output bus, characterized in that, with the aim of increasing noise immunity by completely eliminating false alarms of the device from single emissions of any polarity that do not coincide with the leading edge of the clock, a fifth RS-trigger is introduced into it p, the inverse output of which is connected to an additional R-input of the perBoro RS-flip-flop, the S-input of which is connected to the first-input of the third AND-NOT element and to the first input of the second AND-NOT element, the second input of which is connected to the inverse output of the third RS- a flip-flop whose R-input is connected to the direct output of the second RS-flip-flop, the S-input is from the clock pulse bus, with the R-input of the fourth RS-flip-flop and the third input of the second INE element, the direct output is with the S-input of the second RS-flip-flop, and the second input of the first AND-NOT element, the output of which is connected to the S input of the fourth th RS-flip-flop and the second input of the fourth element AND NOT. the output of which is connected to the second input of the third AND-NOT element, with the third input of the first AND-NOT element connected to the direct output of the fifth RS-trigger, the R-input of which is connected to the direct output of the first RS-trigger, the R-input - with the inverse output of the fourth RS- trigger and output bus, and the input bus is connected to the input of the inverter. Shchig. 2