SU1483617A1 - Device for synchronization and pulse train shaping - Google Patents

Abstract

The invention can be used in devices for synchronizing and forming a series of pulses. The purpose of the invention is to expand the functionality by ensuring the formation of a series of pulses, the duration of which is equal to the period of the pulse frequency. The device contains RS - flip-flop 1, D - flip-flop 2, control bus 4, bus 5 clock pulses, output bus 6. Introduction of an inverter 3 allows the formation of both a single pulse and a series on the output bus depending on the duration of the control signal. pulses, the duration of which is equal to the period of the pulse frequency. 1 sec. f - ly, 1 ill.

Description

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The invention relates to a pulse technique and can be used in systems for processing and generating pulse signals.

The purpose of the invention is to expand the functionality by ensuring the formation of a series of pulses, the duration of which is equal to the period of the pulse frequency.

The drawing shows an electrical functional circuit diagram of the device.

The device for synchronizing and forming a series of pulses contains RS-trigger 1, D-trigger 2, inverter 3, control bus 4, clock bus 5 and output bus 6, the control bus 4 connected to S-BXO trigger house 1, R The input of which is connected to the inverse output of D-flip-flop 2, and the inverse output through inverter 3 to the D-input of flip-flop 2, whose C-input is connected to the bus 5 clock pulses, and the direct output to the output 6.

The device works as follows

In the initial state on bus 4

control signal is absent (unit level). The inverted outputs of the triggers 1 and 2 are single levels. There are zero levels on the direct output of trigger 2, bus 6 and output of the inverter 3. Bus 5 contains clock signals. When an asynchronous control signal arrives on bus 4, trigger 1 is set to S state at the S input. At the same time, the zero level of the inverse output of the trigger 1 is inverted and a single level arrives at the D input of the trigger 2. The trigger 2 on the leading edge of the next clock pulse of the bus 5 is set to one. At the same time, the leading edge of the synchronized pulse is formed on the bus 6. The zero level of the inverse output of trigger 2 acts on trigger 1, returning it to its original state. According to the initial state of the trigger 1 at the output of the inverter 3, the initial state is also set to zero. With the next clock pulse, trigger 2 is switched to the initial state, forming the trailing edge of the synchronized pulse on bus 6. When the next control signal arrives, the device repeats the formation of a synchronized pulse with a duration equal to the period of clock pulses.

If the control signal on bus 4 did not finish at the moment of forming the output synchronized pulse, then the zero level of the inverted output of trigger 2, affecting the R input of the trigger 1, switches only its inverse output to the state of unity. At the same time, its direct output also remains in the state of unity, since the zero control signal is present at the S input. After issuing the first pulse to the bus 6, the trigger 1 is set once again to the single state, forming a zero level at the inverse output at the egms. The device similarly fulfills the second and subsequent pulses. At the end of the control signal, the device returns to its original state,

Consequently, by changing the duration of the control signal, it is possible to form a series of pulses, while controlling the number of pulses of the output series. The duration of the output pulses is equal to the period of the clock signals of the bus 4.

Claims (1)

Invention Formula A device for synchronizing and forming a series of pulses, containing an information bus connected to the S input of the first trigger, a clock pulse bus connected to the BYPASS of the second trigger, the direct output of which is connected to the output bus, characterized in that functionality by ensuring the formation of a series of pulses, the duration of which is equal to the period of the imt, the clock frequency, an inverter is introduced into it, the input is connected to the inverse output of the first trigger, and the output is from D -the input of the second trigger, the inverse output of which is connected to the R input of the first trigger.