SU1192126A1 - Device for synchronizing pulses - Google Patents

Abstract

A DEVICE FOR SYNCHRONIZATION OF PULSES, containing the first trigger, the input of which is connected to the input, and the output is connected to the R input of the second trigger, whose input is connected to the clock bus, and the delay element whose input is connected to the second / second of the second trigger, and the output is connected to the inputs of the first and second triggers, characterized in that, in order to increase reliability, an element AND and an additional trigger are introduced into it, the D-input of which is connected to the output of the second trigger, and the inputs of the element AND are connected respectively о with the output of the additional trigger and the inverse output of the first C of the trigger, the 3-input of which is connected to the output of the element I and R-х x- (L of the additional trigger, the G-input of which is connected to the C-input of the first trigger.

Description

one

The invention relates to a pulse technique and can be used in digital automation devices for matching an asynchronous signal with a clock frequency of a peripheral device.

The aim of the invention is to raise on / off the life of the device.

Fig. 1 shows the function of the device for synchronizing pulses; figure 2 - timing diagrams, his work.

The device contains the first 1 and second 2 triggers, additional trigger 3, delay element 4, element 5, input bus 6 synchronized pulses, bus 7 synchronizing pulses and output bus 8, the inputs of the element 5 also connected to the outputs of the trippers 1,3, ,, the output is connected to the input w of the flip-flops 1.3, the second output of the flip-flop 1 is connected to the input of the flip-flop 2, the output of which is connected to the input of the flip-flop 3 and through the delay element 4 to the input of the flip-flop 2,

The device works as follows

In the initial state, the trigger outputs have one (1) direct output, 3 is inherently low; potential, and at zero (inverse outputs - high potential.

When the pulses are received, the frequency is synchronized across the bus 7 (Fig. 2a, trigger 2 does not switch, because its potential input has a low potential.

The input synchronized pulse generated on the bus 6 phi1.2b, the front edge records the logical unit in the trigger 1

At the direct output of the trigger 1 no H i l a logical unit (FIG. 2Bu, which is fed to the information input of the driver 3. Thereby, the flip-flop 2 is prepared for switching.

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The potential of a logical zero with AND} 1- liepCHoro trigger output 1 blocks the appearance of a signal at the output of an element of the AND 5.

With the arrival on bus 7 of the queue HoiO sy1-timed pulse, 2 switches / fg.2g), the potential of the logical unit is set at its direct output,

About arriving at the output of the device and at the information input of the trigger and through the time determined by the element 4 delay, mouth} sets the trigger1) 1 .; 1 and 2 are reset

5 to -notes.

llnKJi repeats with the arrival of the next synchronized frequency pulse.

The described mode corresponds to

0 also when the input synchronized pulse arrives on the bus 6 after the pulse has terminated on the output bus 8, i.e. when triggers 1 and 2 are set to zero.

In the case of an input synchronized pulse during the pulse on the output bus 8, when the triggers 1 and 2 are set

0 in one state, a logical unit is written to trigger 3 (FIG. 2e), and element 5 is prepared for unlocking.

After the formation of a pulse on the output bus 8, when the triggers 1 and 2 are zeroed, the output of the element And 5 but the signal that returns to the R-input of the trigger 3 and 5 -the input of the trigger 1, sets them to zero and one state.

When the next pulse of the synchronization frequency 5 10 arrives, the bus 7, the trigger 2 switches, and then the process of forming a pulse on the output bus 8 repeats.

Claims (1)

DEVICE FOR SYNCHRONIZING PULSES, containing the first trigger, the input of which is connected to the input bus, and the output is connected to the K-input of the second trigger, the input of which is connected to the bus of synchronizing pulses, and the delay element, the input of which is connected to the output of the second trigger, and the output is connected to the R-inputs of the first and second triggers, characterized in that, in order to increase reliability, an And element and an additional trigger are introduced into it, the D-input of which is connected to the output of the second trigger, and the inputs of the And element are connected respectively to the output of the additional trigger and the inverse output of the first trigger, 3 — the input of which is connected to the output of the And element and the R-input of the additional trigger, the C-input of which is connected to the C-input of the first trigger. -G F ~ L5 neither ΙΓ- f Lq____ g V 3 • 1 _p -J 8 g 4 N _ FIG. t