SU1531185A1 - Pulse synchronizing device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is to improve accuracy while expanding functionality. The device contains triggers 1-3, inverter 4, matching elements 5-8. The introduction of repeater 10 allows one to obtain higher synchronization accuracy due to the coincidence in time of the paraphase signals obtained from the initial sequence, as well as to single out both a single pulse and a series of pulses. 1 il.

Description

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The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to increase accuracy while simultaneously expanding the functionality by forming both a single pulse and a series of pulses.

The drawing shows the electrical functional diagram of the device.

The pulse synchronization device contains the first 1, second 2, third 3 D-type triggers, inverter i, first 5, second 6, third 7, fourth 8 match elements, element OR 9, repeater 10.

The S input of the first trigger 1 is connected to the control bus 11, the D input to the additional control bus 12. The forward output of the second trigger 2 is connected to the first input of the first coincidence element 5, the second input of which is connected to the C input of the second trigger 2 and connected via inverter A to the bus 13 clock pulses, the output to the first input of the element OR 9, the output of which is connected to output bus 14, the second input - with the output of the second coincidence element 6, the first input of which is medium with the direct output of the third tri1-

Gera 3, the R input of which is connected to the output of the third coincidence element 7, the first input of which is connected to the first input of the fourth coincidence element 8, the output of which is connected to the R input of the second trigger 2, the inverse output of which is connected to the second input of the third The first element 7 coincides, and the inverse bit code of the third trigger 3 is connected to the second input of the fourth element 8 coincidence. D-inputs of the second and third flip-flops are connected to the bus of the logical unit, C-input of the third flip-flop is connected via the repeater 10 to the bus 13 clock pulses 1-1 pulses and to the second input of the second coincident element 6 coincidence 5t. The C input of the first trigger is connected to the output of the element OR 9.

The device works as follows.

In the initial state, the triggers 1-3 are in the zero state, on the device bus 11 - high, the clock pulses from the bus 13 through the inverter 4 and the repeater 10 arrive at the C inputs of the flip-flops 2 and 3

respectively, but do not cause their installation in the single state, since the R-inputs of the flip-flops 2, 3 through the elements 8 and 7 from the output of the flip-flop 1 receive low potentials. On the bus 14 devices - high potential.

Suppose chtp bus 12 devices - low potential. When a negative impulse device arrives on bus 11, trigger 1 is set to one. Depending on whether the trigger signal 1 was set to a single state coincided with a negative or positive half-wave clock signal, one sets trigger 2 or 3, respectively.

Let the coincidence happen with a low level of negative half-wave of the clock signal, then trigger 2 at the end of a low level of negative half-wave at the output of inverter 4 is set to one state and allows through element 5 the passage of the negative half-wave of the clock signal. The low potential from the zero output of trigger 2 through element 7 prohibits the installation in one state of trigger 3 and it retains its zero state. The signal from the output of the element 5 through the element 9 is fed to the bus 14 of the device and the C input of the trigger 1.

Upon completion of the signal at the output of element 9, the trigger 1 is set to the initial zero state and through element 8 sets the initial zero state to trigger 2. At the same time, the further passage of clock signals through element 5, element 9 to the bus 14 of the device is prohibited. If the moment when trigger 1 was set to one state coincided with a low level of the positive half-wave of the clock signal at repeater 10 output, trigger one is set to trigger state 3. Trigger 3 with elements 7 and D is similar to trigger 2 with elements 8 and 5 s. the difference is that the device bus 14 receives a signal synchronized with a positive half-wave clock signal.

Suppose now that on the bus 12 devices - high potential. Then, when a negative pulse device arrives on bus 11, elements 1–9 work similarly to the one described above until the end of the first signal on

bus 1A device. Upon completion of the signal on bus 14 of device 1, trigger 1 is not reset to its original zero state, since its D input has a high potential, which means one of triggers 2 or 3 is not reset to zero and clock signals are not allowed to pass through the elements 5 , 9 or 6, 9 on the bus 14 device. Clock signals arrive at the device bus 14 until a negative pulse arrives at the device bus 12. When it coincides with the end of the next clock signal on the bus 14 of the device, the trigger 1 is reset to the initial zero state, which causes the initial state of the entire device to be reset.

Thus, if there is a low potential device on bus 12 and a negative pulse arrives on bus 11 at output 14 of the for10 device

the first of which is connected to the control bus, the direct output of the second trigger to the first input of the first coincidence element, the second input of which through the inverter is connected to the clock pulse bus, the output to the first input of the OR element whose output is connected to the output bus, the second input - with the output of the second element, a match, the first input of which is connected to the direct output of the third trigger, the R input of which is connected to the output of the third match element, 15 the first input of which is connected to the first input of the fourth match element, the output of which is connected to the R-input of the second trigger, characterized in that, in order to increase accuracy with simultaneous expansion of functionality, a repeater is introduced into it, an additional control bus, the first, second, third D20 triggers

A single signal is synchronized, type-25 sync-low, the D input of the first of which is connected to the additional control bus, the C input - with the output of the IPI element, the direct output - with the first input of the fourth element coincides 1 "1, the second input

with clock signals on the bus 13 of the device, and if there is a high potential device on the bus 12 with a negative on the bus 11

pulse on the bus 14 of the device which is 30 is connected to the inverse output

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the first of which is connected to the control bus, the direct output of the second trigger to the first input of the first coincidence element, the second input of which through the inverter is connected to the clock pulse bus, the output to the first input of the OR element whose output is connected to the output bus, the second input - with the output of the second element, a match, the first input of which is connected to the direct output of the third trigger, the R input of which is connected to the output of the third match element, 5 the first input of which is connected to the first input of the fourth match element, the output of which is connected to the R-input of the second trigger, characterized in that, in order to improve accuracy with simultaneous expansion of functionality, a repeater is introduced into it, an additional control bus, the first, second, third triggers D

The sequence of clock signals starts, the start of which is synchronized with the arrival of a negative pulse on the device bus 11, and the end with the arrival of a negative pulse on the bus 12 of the device.

Claims (1)

Invention Formula Pulse synchronization device containing three three H-ers, S-input the third trigger, the C input of which is connected to the clock pulse bus through the repeater and to the second input of the second coincidence element, the second input of the third coincidence element connected to the inverse output of the second tripra, the C input of which is connected to the second input of the first matching element, D- The inputs of the second and third triggers are connected to the bus of a logical unit.