SU1311018A1 - Pulse repetition frequency divider with 3:1 countdown - Google Patents

Description

The invention relates to a pulse technique and can be used in automation devices and computing.

The purpose of the invention is to expand the functionality by providing a pre-installation of the device to its original state and increasing the symmetry of the output pulses;

The drawing shows an electrical functional diagram of the proposed device.

The impulse frequency following divider into three contains B trigger 1, the direct output of which is connected to J-BXO- the house of JK-trigger 2, whose K-input is connected to its direct output, the inverse output to the S-input of D-trigger D- the input of which is connected to its inverse output. The C and R inputs of both triggers are connected to the input bus 3 and to the reset bus 4, respectively. The signals at the outputs of D-flip-flop 1 and JK-flip-flop 2 are used as Vigo signals.

The frequency divider works as follows.

The device is set to the initial (zero) state by applying a zero level to the pin 4.

On the front of the first pulse on the 3 V bus, the trigger I is set to one. By the cut of this

Editor M. Bandura

Compiled by A.Sokolov

Tehred M. Khodanich Proofreader G. Reshetnik

Order 1902/55 Circulation 902 Subscription

VNIIPI USSR State Committee

on the case of inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

torus

pulse JK-flip-flop 2 is also set to one state and the zero level from its inverse output to the S-input of D-flip-flop I, will block switching of the latter from the front of the second pulse on bus 3 By cutting the second pulse on bus 3 JK-trigger 2 returns to its original state. lio the front of the third pulse on bus 3; D flip-flop I also returns to its initial state; at the cut of this pulse, the state of JK flip-flop 2 does not change.

Further, the cycle of operation of the device is repeated.

Claims (1)

Invention Formula A pulse frequency divider by three, containing a D-flip-flop, the direct output of which is connected to the J-input of a JK-flip-flop, whose C-input is connected to the C-input of a D-flip-flop and to the input bus, characterized in that functionality and improve the symmetry of the output pulses, a reset bus is inserted into it, which is connected to the R input of the D trigger and to the R input of a JK trigger, whose direct output is connected to its K input, the inverse output to the S input D-flip-flop, the D-input of which is connected to its inverse output.