SU1420655A1 - Device for subtracting pulse trains - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation, instrument making and computer engineering. The aim of the invention is to increase the reliability of the device, which is achieved by simplifying it as a result of the proposed construction scheme. The drawing shows the D-flip-flops 1, 2 and 3, the element is NOT 4, the element AND-KE 5. When the device is working, when the frequency of the pulses on the second input bus exceeds the frequency of the pulses on the first input bus, the D-input of the trigger 3 there will be a constant level of logical O and, as a result, at the output of trigger 3 there will always be a logical level of O. That is, no pulses will appear on the output bus of the device. The accuracy of the device is maintained in a wide range of frequencies and signal durations of the input pulse sequences. 2 Il. § (/)

Description

4 S

O) JV SL

QDi / e. 7

The invention relates to a pulse technique and can be used in automation, instrument making and computing technology. The purpose of the invention is to increase the reliability of the device by simplifying it.

FIG. Figure 1 shows the electrical structure of the device; on Fig 2 - timing charts for c - and his work.

The device (Fig. 1) contains the first trigger 1, the direct output of which is connected to the D inputs of the second and third triggers 2 and 3, and the C input of the trigger 3 is connected to the input of the HE element 4, the C input of the trigger 2 and the first the input bus, and the output with the output bus and the first input of the element AND-NOT 5, the second input of which is connected to the output of the HE 4 element, and the output to the R input of the trigger 3. The C input of the trigger 1 is connected to the second input bus, D -input - with common bus, inverse output - with S-input of trigger 2, and S- input - with output of trigger 2.

FIG. 2 shows the following time diagrams: a - pulse sequence on the first input bus; b - pulse sequence on the second input bus; c - signals at the forward output of flip-flop 1; g - signals at the direct output of trigger 2; d - signals on the output bus.

The device works as follows.

The initial state of the triggers 1 and 2 is single, i.e. at the direct outputs there is 1, the trigger 3 is zero.

Consider the case when the frequency of the pulses on the first input bus is greater than on the second input bus, i.e. normal case. Since there is 1 on the D-input of the trigger 3, when the front edge of the pulse appears at the first input bus, the output of the trigger 3 appears 1. When the pulse ends on the first input bus, and the appearance of O at the output of the I- NOT 5, the trigger 3 is transferred to the state O, - In fact, the pulse at the output of the trigger 3 repeats in duration the pulse on the first input bus. When a pulse appears on the second input bus, trigger 1 is set to state O, and

it means that O appears at the D inputs of triggers 2 and 3. When a pulse appears on the first input bus, its leading edge sets the output of triggers 2 and 3 to level O. Actually nothing changes at the output of trigger 3, i.e. pulse from the first input bus to the output bus does not pass. At the output of trigger 2, a transition from state 1 to O. occurs. This transition transfers trigger 1 via the S input to state 1.

O, having appeared on the inverse output of flip-flop 1, returns flip-flop 2 via S-input also to state 1. As a result, the pulse is subtracted on the first input bus by the pulse previously generated on the second input bus. .

When the frequency of the pulses on the second input bus exceeds the frequency of the pulses on the first input bus, a level O is constantly present at the D input of trigger 3 and, as a result, there is O at the output of trigger 3. no impulses appear on the output bus of the device.

The accuracy of the operation of the described object is maintained in a wide range of frequencies and signal durations of the input pulse sequences.

Claims (1)

Invention Formula A device for subtracting pulse sequences containing the first trigger, the direct output of which is connected to the input of the second trigger; The input of which is connected to the first input bus — the input of the element HE and the input of the third trigger — whose output is connected to the first input of the element I- NOT, and the C-input of the first trigger is connected to the second input bus, as well as the output bus, of which is connected. In order to improve device reliability by simplifying it, the D input of the first trigger is connected to the common bus, the S input is connected to the direct output of the second trigger, the inverse output is connected to the S input of the second trigger, and D-input of the third trigger, the output of which is connected to the output bus, and the R-input to the output of the NAND element, the second input of which is connected to the output of the NO element, Fi.g