SU748832A1 - Single-pulse shaper - Google Patents

Description

one

The invention relates to radio engineering and can be used in automation and computer devices. . . A known generator of single pulses, containing a trigger with separate inputs, a logical element And, a three-push button switch and a delay line Sc ..

However, the known device has a low reliability and stability due to the presence of a delay line.

The closest technical solution to the invention is a single pulse shaper, which includes the trigger trigger, the inputs of which are connected to the contacts of the logic switch, the input and MULTI triggers, the four NAND logic elements, feedback trigger 2. This shaper is complicated.

The aim of the invention is to simplify the former and increase the reliability of its operation. The goal is achieved by the fact that in a single pulse shaper containing a trigger trigger, the inputs of which are connected to the contacts of a logic switch, a reverse trigger trigger

connection, the output trigger and the two elements IS-NOT, the output of the trigger trigger is connected to the first input of the I output trigger and the input of the first AND-NOT element whose output is connected to the first input of the second AND-NOT element, the second input connected to the second input 1 and the first input To the output trigger and clock source, the output of the second element is NOT connected to the feedback trigger input, the output of which is connected to the third input I of the output trigger, the direct output of the latter is connected to its own second input K, and the inverse output - with the second input of the feedback trigger.

The drawing shows a functional diagram of a single pulse former.

The single pulse shaper contains trigger 1, the switch contacts 2 of the logic signal, the first 3 and second 4 AND-NOT elements, the output trigger 5, and the feedback trigger 6.

Shaper single pulse works as follows.

In the initial state, from the contacts of the switch 2 to the input of the trigger of trigger 1 the signal is received. units, and from the output, its logical zero arrives at the input f of the output trigger 5 and prohibits its triggering from the clock frequency, incoming Ea input 7, as well as the AND-NOT 3 element working as an inverter. The potential at its output permits the passage of a clock frequency through an AND-HE 4 element to the input of the feedback trigger b and sets it back to its initial state (f g „a“ switch) -.

When switching contacts of switch 2, a potential arises at the output of trigger 1, permitting the operation of output trigger 5 from the trailing edge of the first clock pulse and prohibiting the passage of the clock frequency to the input, feedback trigger 6. When the output trigger is triggered, a potential arises at its inverse output that flips the feedback trigger to another state. The second clock pulse returns the output trigger to the initial state. Thus, at output 8, a pulse is generated, which is equal in duration to the period of the clock frequency. When applied to the trigger trigger input from the logical zero switch contacts, a clock frequency pulse is applied to the feedback trigger and returns it to its original state.

This driver can be used in computing devices and synchronization systems. Its use reduces the cost of these devices and increases the reliability of their work as a whole.

Claims (1)

1. USSR author's certificate No. 493008, cl. H 03 K 3/78, 19752. Author's certificate of the USSR No. 528693, cl. H 03 K 3/78, 01.10.7. 7