SU1444931A2 - Pulser - Google Patents

Abstract

The invention relates to microelectronics and can be used in digital signal processing devices. The purpose of the invention, the extension of functionality, is achieved by generating a series of output pulses of various frequencies along the leading and falling edge of the control signal. For this, the pulse former 1 and the corresponding functional connections are additionally introduced into the generator. The pulse generator also contains an input bus 2, elements EXCLUSIVE OR 3 and 5, a counting trigger 4, output 6, a delay element 7. By introducing new elements and connections, a series of output pulses of various frequencies are generated at the front and decay of the control signal, as a result of which the functionality of the generator expands, for example, it can work as a frequency manipulator. 1 il. (L

Description

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The invention relates to microelectronics, can be used in devices. Digital signal processing and is additional to the author. St. W 1228246.

The aim of the invention is to extend the functionality by generating a series of impulse pulses of various frequencies on the front and the decay of the control signal.

The goal is achieved through the introduction of a pulse former and new communication.

The drawing shows a structural, Electrical pulse generator circuit.

The pulse generator contains the pulse shaper 1, the input of which is connected to the input pin 2, and the output to the first input of the EXCLUSIVE OR 3 element, the counting trigger 4, the C input of which is connected to the output of the EXCLUSIVE AND OR 5 element, the R input with the output of the forcing 1 pulses, and the output - with the second inputs of the elements EXCEPT OR 3 and 5 and the output bus 6, the delay element 7, the input of which is connected to the output of the EXCLUSIVE OR 3 element, the output - to the first input of the EXCLUSIVE OR element 5,

and the control input is with input bus 2..

The pulse generator works as follows.

The device is reset to its initial state by applying a zeroing pulse to an additional R input (not shown) of trigger 4. In this case, the outputs of the pulse former 1 of the pulses of the EXCLUSIVE OR 3 and 5 elements and the delay element 7 present the logic level 1, and at the output of the counting trigger 4 - level of logical p.

The input control signal from the input bus 2 is fed to the input of the pulse former 1, at the output of which the leading polarity and decay of the input signal generate negative polarity pulses, the duration of which must be at least half the period of the shortest frequency.

Suppose ka input bus 2 enters the front of the control signal. When the first pulse ends - formed by the pulse shaper 1, the lock is released from the R input

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trigger 4. In addition, a negative polarity pulse from the output of the former I pulse through the elements EXCLUSIVE OR 3, the delay element 7 and the EXCLUSIVE OR element 5 is fed to the C input of the counting trigger 4, translating it along a positive differential into the opposite single state. From the output of the counting trigger 4, a high level enters the inputs of the elements EXCLUDING OR 3 or 5, the outputs of which are set to zero.

The delay generated by the delay element 7 depends on the level of the control signal supplied to the input bus 2. With a high level of the control signal of the input 2, the delay element 7 generates a delay ZTj, and at a low level it delays t. Delay element 7 can be implemented by well-known schemes, for example, using two series-connected delay units, whose outputs are connected to the information inputs of the switch, the output of which is the output of delay element 7, and the control input - control input Cement 7 delay.

After the first switching of the counting trigger 4 from the zero state to one at the outputs of the EXCLUSIVE OR elements 3 and 5, the signal level is set to zero. At the same time, the zero level of the signal from the output of the EXCLUSIVE OR 3 element with a delay on the delay element 7 enters the input of the EXCLUSIVE OR element 5, which causes a high signal level at its output. The positive differential of the pulse signal at the C input of the counting trigger 4 performs its sequential switching, in this case to the zero state. The zero level of the signal, arriving at the second inputs of the elements of the IC - EXCLUSIVE OR 3 and 5, leads to the appearance of N and their outputs, respectively, of the unit and zero levels. The unit level from the output of an EXCLUSIVE OR 3 element with a delay on the delay element 7 (in this case with a delay C,) enters the input of the EXCLUSIVE ITS OR 5 element, which results in a positive voltage drop at its output, which, in turn, provides

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switching countable triggered

Hera 4. In the following, the operation of the device is cyclically repeated. In this case, the generation of a series of output pulses with a follow-up period of 2 ° C is ensured (without taking into account delays, trigger the device elements).

By the decay of the input control signal, the pulse shaper 1 forms an impul1 from a low level, which zeroed the counting trigger 4, and at the same time, the delay element 7 is switched from delay b, to

delay about

At the end of the reset pulse, the unit level removes the blocking from the R input of the counting trigger 4. After this, the device operates as in the case considered, and on the output bus 6 a series of pulses is issued with a follow-up period equal to

2-6 ,.

By introducing new elements and connections into the device, a series of serial pulses of different frequencies are generated at the leading edge and decay of the input control signal, as a result, the functionality of the pulse generator and its scope can be expanded, and it can operate as a frequency manipulator.

Claims (1)

Invention Formula Pulse generator auth. St. No. 1228246, characterized in that, in order to expand the functionality by generating a series of output pulses of various frequencies at the front and decay of the control signal, a pulse driver is inputted into it, the input of which is connected to the input bus and the control input of the delay element, and the output . with the first input of the first element EXCLUSIVE OR.