SU738175A1 - Divider of pulse repetition frequency by five - Google Patents

Description

(54) REPLACEMENT FREQUENCY DIVIDER

PULSES FOR FIVE

In PG S

. ". .-J. I

il3lia i: ucicrI3i

The invention relates to pulsed and computational and can be used in functional units of computing devices.

A scaling device is known which can perform the operation of dividing the repetition frequency by five, performed on the potentized triggers, containing AND, NOT, OR elements and control and reverse units 1,

The disadvantage of this device is its relative complexity.

The closest in technical essence to the invention is a pulse repetition frequency divider for five that contains potential triggers with separate inputs, an output element And and an inverter, the input of which, one of the inputs elemena And, both inputs of the second and zero input of the fourth potential trigger are connected to input bus, and the inverter output is connected to the inputs of the first potential trigger and to the single input of the third and to the zero input of the fourth potential trigger, and the single output of the first potential trigger with The single and zero inputs are the second and the fourth, and the south output with single inputs of a second and fourth potential trigger, the third output of the third is connected to zero inputs of the first and second, and its zero output is a single input of the second potential trigger and the second input of the output element And, the third input of which is Diyen's soybean with a single output of the first potential 10 trigger, the single output of the fourth trigger is connected to the zero input of the second and to the single input of the third, and zero input to the single input One and the third entrance of the house of the third 12.

The disadvantage of this divider is its relative weakness, ITO is accompanied by a low reliability of its operation. :

20

The purpose of the invention is to increase the reliability of the work of the divider.

For this purpose, in the frequency divider. Repetition of pulses into five, containing a potential trigger lag with a frequency, are located in the inputs, the output element of the | nd inputs of which are connected to unity. to the first output of the first potential trigger and to the input bus to which it is connected; second potential inputs30

.; i; "wi i" aiiw "iwE Troi" Jsii; e4, .. ,,

, 7 -; .- V- - - / - -b

YOGO Trigger, and the inverter, whose input is connected to the input jiraWe, and the output is connected to the zero input of the first potential trigger, the single output of which is connected to the zero input of the second, and the zero output Y-SHYBD to the single input of the second and fourth potential triggers, the zero output of which is connected to the Zero input of the third, and the single output to the zero Bxow / of the second potential trigger, the zero output of which is connected to the zero input of the first potential trigger; the zero input of the first potential trigger of the connection n with single outputs and second and third output with zero and W TlfeTbero chetvortogb by oyShaL: N1H triggers tret- input unit,

 A potential trigger is connected to the single outputs of the first and second potential triggers and to the input bus, the zero input is with a zero output of the third potential trigger and the input bus, and the zero outputs from the second and fourth potential triggers, the single input of the last, of which is connected to the input bus and zero is connected to the output of the inverter, connected to the inputs of the output element. Structural electrical circuit of the pulse-frequency divider. Five in the figure. The divider contains potentiald triggers, 1-4, the first of which contains the logical elements NOT and AND-OR-NOT, and the rest - two logs jfeSKHX of the element X-OR-NOT, each. also the inverter S- to the output element AND 6.

Potential triggers that are included in the divider, the pulse repetition frequency by five, switch the ori mry account Mx NB e in phase-shifted 180. Ishb nm

The device state is the presence of a negative (single) potential at the zero outputs of the flip-flops and at the output of the inverter 5.

Divider works following oiSpazom. .

With the coming of the first impulse of sleep-. 1 start of the VITS unit potential at the input of the device, and in the upcoming trigger 2 changes its status, the trigger shows the negative potential at the output of the inverter 5, and the first trigger 1 changes its state.

When the second pulse arrives, a single potential is reached at the input of the device, and the third is triggered. The state changes, the negative potential appears at the output of inverter 5, and the first trigger 1 returns to its original state.

With the arrival of the third pulse

Initially, there is a 1 ps unit potential at the input of the device, and the fourth trigger 4 changes its state, beyond 7,38175

That is, there is a single potential at the output of the inverter 5, and the first trigger 1 changes its state.

With the arrival of the fourth pulse, the unit potential at the input of the device first appears, and the second trigger 2 returns to the initial state, then the unit potential appears at the output of the inverter 5, and the fourth pulse 4 returns to the initial state. When the fifth pulse arrives, start with a unit potential at the input of the device, and the third trigger 3 returns to its original state, and the output element, And b, also goes to the device output, then goes, the unit potential at the output of the inverter 5, and the first trigger 1 returns to the outgoing state, with the entire circuit returning to the initial state

Claims (2)

1. USSR author's certificate No. 254230, cl. H 03 K 23/24, 1970.  2. USSR author's certificate 534874, cl. H 03 K 23/02, 1975. (prototype).