SU832715A1 - Pulse monitoring device - Google Patents

Description

(54) DEVICE FOR PULSE CONTROL

Claims (2)

The invention relates to a pulse technique, namely to pulse control devices. A device for controlling pulses is known, which contains an input element OR, an RS flip-flop, logic gates And connected to the input buses, an RS flip-flop input and each other .l However, the device does not provide sufficient control accuracy. The closest to the invention to the technical essence is a pulse control device containing the first element AND, one of the inputs of which is connected to the source of controlled pulses, the second input of the first element AND is connected to the first source of clock pulses, and the output of the first element AND is connected to the first input the first trigger whose output is connected to one of the inputs of the second element And, the second input of which is connected to the second source of clock pulses, and the output of the second element And is connected to the first input of the second trigger, the output of which is connected to one of the inputs of the third element And, the second input of which is connected to the third clock source, and the output of the third element And is connected to the second input of the first trigger, the second input of the second trigger is connected to the second input of the first element II. device is its complexity. The purpose of the invention is to simplify the device. The goal is achieved by the fact that the device contains two O-triggers and an element, whose inputs are connected to the outputs of the D-triggers, the R-inputs of each of which are connected to the output of the element And, O-input of the first and C-input of the second O Triggers are connected to the monitored signal bus, S-inputs of both 0-triggers are connected to the first clock signal bus, the AC input of the first and D-input of the second Ot-flip-flop are connected to the buses of the second and third clock signals. The drawing shows a structural electrical circuit of the proposed device. The device contains the first 1 and second 2 0.-triggers, 3 epements And, on the input bus 4 is fed a controlled pulse sequence. On the bus 5-7 served clock signals. The output signals are removed from output 8. The operation of the device is carried out as follows. In the initial state, by means of a single pulse on the bus 5, the device is set to the initial state, triggers 1 and 2 are in the unit state, at their outputs and, therefore, at the output of element 3 And and output 8 of the Device, high level potentials. At the end of the clock pulse bus 5, the device is ready for operation. When a clock pulse arrives on bus 7 (clock pulses on bus 7 advance the expected pulses of the monitored sequence) at the D input of trigger 2, it sets a high potential level. When a monitored pulse arrives on the device bus 4, which coincides with the clock pulse on bus 7, the unit state of the trigger 2 is confirmed, since at its D-input at this time there is a high (single) level. Upon receipt of a clock pulse on bus 6 (clock pulses on bus b are delayed relative to the expected pulses of the monitored sequence) the unit state of trigger 1 is confirmed, since at its time there is a high level potential on its D input. Thus, in the presence of a controlled pulse, the incoming clock pulses on tires 6 and 7 confirm the initial states of triggers 1 and 2 and, therefore, a high level is maintained at the output 8 of the device, i.e. health state. Upon receipt of the next clock pulse on the bus 7 and the absence of a controlled pulse, the state of the trigger 2 does not change, since there is no impulse along its synchronization course, and a high level potential at the O input. When a clock pulse arrives through bus 6, trigger 1 is switched, since its O-input has a low (zero) level at this time. At the output of the trigger 1 and, therefore, at the element 3 And and the output 8 of the device it sets to the low potential level (fault state), signaling the absence of Iltulse in a controlled sequence. In addition, the potential of low ur. n from the output of element 3 And the R input of trigger 1 arrives, confirming zero state of trigger 1, switching trigger 2 to zero state and preventing their possible switching by pulses coming in on buses 4, 6 and 7. The potential low level (state of failure) at the output 8 of the device is preserved until an act pulse arrives on the bus 5, setting the triggers 1 and 2 to one state, i.e. the device returns to its original state. By the end of the pulse on the bus 5, the device is ready for operation. Upon receipt of the following clock pulses and the presence of controlled pulses on buses 4, 6 and 7, the state of the flip-flops 1 and 2 and the device as a whole does not change and the operation of the device is as described. When an excess pulse arrives on the bus 4 in a controlled sequence (for example, a pulse spontaneously formed at the source of controlled pulses), trigger 2 switches to the zero state, because at its D input at this time point there is a low (zero) level potential. At the output of the trigger 2, as well as the output of the element 3 And and the output 8 of the device, a low (zero) level potential is set to indicate the presence of an excess (Extra) pulse in the monitored pulse sequence. In addition, from the output of element 3, the low-level potential enters the R-inputs of flip-flops 1 and 2, confirming the zero state of flip-flop 2, switching to the zero state flip-flop 1 and preventing their possible switchings by incoming pulses on buses 4, 6 and 7. Therefore, upon receipt of pulses on buses 4, 6 and 7, the state of the device does not change. When an alternate clock pulse arrives on bus 5, the triggers 1 and 2 are set to one and the device returns to its original state, after which the work cycle is repeated. Claims An impulse control device comprising two D triggers and an element, whose inputs are connected to outputs of Dt-flip-flops, the R inputs of each of which are connected to the output of an element And, characterized in that, in order to simplify the device, the D input of the first D-trigger and C-input of the second 0-trigger are connected to the controlled signal bus, S-inputs of both D.-flip-flops are connected to the bus of the first clock signal, and C-input of the first and D-input of the second 0, -triggers are connected to tires second and third clock signals. Sources of information taken into account in the examination 1. For the Germany, No. 2038211, cl. H 03 K 5/18, 03/17/77. 2. Authors certificate USSR 599341, cl. H 03 K 5/18, 12.12.76 ..