SU1338023A1 - Pulse former - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for automation and computer technology, in particular, for generating pulses. The purpose of the invention — the simplification of the device — is achieved by reducing the hardware costs while retaining the functionality of the device for generating single or paired pulses of a certain duration. For this purpose, the second element IS-HE 5 and the corresponding functional connections between the circuit elements are additionally introduced into the device. The device contains the element AND NOT 1, triggers 2 and 3, the element 4 delay, input 6 and 7 and output 8 tires. The operation of the pulse former is explained in the timing diagrams provided in the specification. 2 Il. with (L with with 00 o y oo (rig.1

Description

1lj (J8023

The invention relates to a pulse technique and can be used in automation and computing devices, in particular, for the formation of clock pulses.

The purpose of the invention is to simplify the device by reducing hardware costs while maintaining the functionality of the device for generating single or paired pulses of a certain duration.

FIG. 1 shows a functional diagram of a pulse former; in fig. 2 - time diagrams, according to IS 5, from the second input bus 7, those who remove it work; level 1. As the fourth

level O is formed (fig. 2d). When switching the trigger 3 level O from its direct output through :) the element 4 of the delay, with the delay time T, arrives at the second input of the first element AND-IE I. At the output of the latter, level 1 (Fig. 2c) appears, arriving at the R input of the second trigger 3, the output bus of the device, and the second input of the second element NAND 5. Let the device generate pair pulses. In this case, the third input of the second element is NOT

The pulse shaper contains the first element AND-iiE 1, the first 2 and second 3 triggers, the delay element 4, the second element IS-HE 5, nepByjij 6 and the second 7 input bus, output bus 8. The first input bus 6 is connected to the first inputs of the first 1 and the second 5 IS-NOT elements, the R input of the first trigger 2, 3 to the input and D input of the second trigger 3. The output of the second trigger 3 is connected to the C input of the first trigger 2 and through delay element 4 to the second input of the first element AND-NOT 1. The output of the first element AND-NOT 1 is connected to the output bus 8 and the second input of the second element AND-NOT 5. Tr Tille input of the second AND-NO element 5 is connected to a second input bus 7, and a fourth input - to the D-input and an inverse output of the first flip-flop 2.

The pulse shaper operates as follows.

In the initial state, when there is no input signal on the first input bus 6, level O, which drives the first trigger 2 on the inverse output and the second trigger 3 to state 1. On the second (control) input bus 7, level 1 when generating paired pulses (interval , i, fig. 2) and level O at the formation of single pulses (interval tj-t,, fig. 2).

When a single impulse arrives at the first input bus 6 of the device (Fig. 2a) at the R input of the first trigger, the S and D inputs of the second trigger 3 and the first inputs of the first 1 and second 5 AND-NOT elements appear level 1 , and at the output of the first element AND –NE 1, the level O (Fig. 2p) causes the switching of the second trigger 3, the direct output of which

-

5 from the second input bus 7 enters level 1. Since the fourth

level O is formed (fig. 2d). When switching the trigger 3 level O from its direct output through :) the element 4 of the delay, with the delay time T, arrives at the second input of the first element AND-IE I. At the output of the latter, level 1 (Fig. 2c) appears, arriving at the R input of the second trigger 3, the output bus of the device, and the second input of the second AND-NOT element 5. Let the device generate paired pulses. In this case, the third input of the second element is NOT

20

thirty

the input of the second element IS-HE 5 from the inverse output of the first trigger 2 enters level I (Fig. 2e), then the output of the element IS-HE 5 forms the level O (Fig. 2d), which arrives at the C input of the second trigger 3 and causes to the negative signal front, switching of trigger 3. At the forward output of trigger 3, a level 1 is formed (Fig. 2e), which arrives at the C input of the first trigger 2 and through delay element 4 to the second input of the first AND-1 element. The C input of trigger 2 at its inverse output forms a level O (FIG. 2 e), a step The fourth input of the second element AND-NOT 5 and blocking the passage of the signal to the C input of the second trigger 3 is output. At the output of the first element AND 1 NO 1, a second output pulse of duration D (FIG. 2c) is formed, and at the forward output of trigger 3 level Oh coming through

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element 4 of the delay at the second input of the first element AND-NOT 1. At the output of the last, a level 1 appears, which arrives at the second input of the second element AND-NOT 5. At the same time, the level O does not form at the output of the element AND-NOT 5, since its fourth input, level O. Trigger 2 does not switch and at its inverse output level O is maintained.

If the level and on the second input bus 7 of the device (tj-t interval of Fig. 26}, then upon receipt of a single input pulse (Fig. 2a), the output O of the first element of the N-1 1 is generated at the output 55 of the first element IS-NOT 1 3, the output bus 8 of the device and the first input of the second element NAND 5. At the output of the second 50

The level O (Fig. 2e) is formed through the triangular element 3, which arrives through the delay element 4 at the second input of the first AND-1 element. At the output of the AND-1 element 1, level 1 is formed (Fig. 2c) received at the R-input trigger 3, the output bus 8 and the second input of the second element AND-NOT 5. At the output of the element AND-NOT 5, the O level is not formed, since the third input of the AND-NOT 5 element is O, blocking the C signal input second trigger 3. Triggers 2 and 3 do not switch and the corresponding

On their inverse and direct outputs, levels O and 1 are preserved, and one pulse is formed on the output bus 8 of the device (Fig. 2c).

The end of the input single impulse D1VIVODITs to return to the initial state of the first 2 and second 3 triggers and the output at the output of the first AND-NO 1 level 1.

Compiled by A.Orechny Editor N.Kishtulinets Tehred M, DIDIKKorrektor S.Shekmar

41AZ / 54 order

Circulation 901 Subscription

VNISh State Committee of the USSR

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

0

five

3

Claims (1)

An inventive pulse shaper comprising a first NAND element, a first input connected to a first input bus and an R input of a first trigger, a second input bus, a second trigger, and a delay element, characterized in that, in order to simplify the device, a second the NAND element, the first input of which is connected to the first input of the first NAND element, with the B input and the D input of the second trigger, the output of which is connected to the C input of the first trigger and through the delay element to the second input of the first AND element NOT, the output of which Nen to the output bus and a second input of the second AND-NO element whose output is connected to the C-input of the second flip-flop, the third input - to a second input bus, the fourth input - to the D-input and an inverse output of the first flip-flop.