SU1714630A1 - Test pulse generator - Google Patents

Abstract

The invention relates to computer science and computing, and can be used in test diagnostics systems or in embedded self-test devices as a programmable driver of test effects of channel electronics. The purpose of the invention is to increase the rate of formation of pulsed test effects. This goal is achieved by what's in the device containing the 1K trigger. OR-NOT elements and a modulo-two adder are introduced, which ensures that in two * {EaZa faster response times for the formation of pulsed test signals. 1 or 1 table. 1. The invention relates to automation and computer technology and can be used in test diagnostics systems as a programmable test action generator. The purpose of the invention is to increase the speed of formation of pulse test effects. The drawing shows a diagram of the proposed device. The device contains a trigger 1. informational inputs 2 and 3 of the trigger 1. sync-move 4 of the trigger 1, element OR NOT 6. element AND 6. adder 7 modulo two and output 8 of the device. The device works as follows .On data inputs 2 and 3, the device enters codeword (command) defining the rabotyustroystva mode in the next cycle. When the clock signal arrives at the sync input 4 of the device at its output 8, the next test action is formed, the nature of which is determined by the current state at inputs 2 and 3 of the device and the current state of trigger 1 in accordance with the table below. It can be seen that when the command "10" is received at the inputs 2 and 3 of the device with the arrival of the sync signal on the synchronous input 4 of the device, the logical unit is written to the trigger 1, regardless of its current state, which was set to m tact work. The presence of a logical unit at any of the inputs of the logical element OR — NOT 5 provides a zero state at its output, which, acting on the second input of the logical element AND 6, prohibits the pro-4 ^ O))

Description

the clock signal to the output device from its sync.

The zero state from the output of the logic element And b goes to the second input of the adder 7 modulo two, ensuring its operation in the repeater mode of the logical signal coming from the output of the trigger 1 through its input 2 to the output 8 of the device.

When command 01 is received at the inputs 2 and 3 of the device with the arrival of the sync signal at the sync input 4 of the device, the logical zero is written to the trigger 1, regardless of its current state. The value of the logical zero from the trigger output goes to the output of the device through the adder 7 modulo two, which in this case also works in the mode of repeating the output signal of the trigger 1.

When a command 11 arrives at the inputs 2 and 3 of the device with the arrival of the sync signal at the sync input 4 of the device, the current state of trigger 1 is inverted and transmitted to the output 8 of the device. The remaining actions are the same as for commands 01 and 10.

When command 00 arrives at the device inputs 2 and 3, the current state of trigger 1 does not change with the arrival of the sync signal at sync input 4. The zero state at both inputs of the OR-NO 5 logic element forms a single state at its output, which the input of the logical element And b, provides the passage of the sync signal from the sync input 4 through the first input of the logical element And 6 to its output. If the current state of the trigger 1 is zero, then it arrives modulo two at the first input of the adder 7, allows the clock signal from the output of the logic element AND 6 to pass through the modulo two of the second input without inversion and produces a positive test pulse at input 8 devices.

Otherwise, when the current state of the flip-flop 1.- is single, it arrives modulo two at the first input of the adder 7. It provides the passage of a sync signal from the output of the logic element. And b modulo two with the inversion of the second input of the adder 7 and the formation of a negative pulse test effect on the output 8 of the device.

Thus, the introduction of logical elements OR-NOT 5, Ib, adder 7 modulo-two with its own connections provides twice as much speed as the formation of pulse signals, since the formation of a single pulse signal requires one command to form a pulse action, followed by one clock signal, while in a known device a sequence of two commands and two clock signals would be required for this.

Claims (1)

Invention Formula A device for generating test actions, which contains a K-trigger, the information and K-inputs of which are the inputs for setting the operating mode of the device, the synchronous input of the K-trigger, is a synchronous input of the device, characterized in that, in order to increase the rate of formation of impulse test effects, entered elements ILINE, element AND, a modulo-two adder, the output of which is the test output of the device, the first and second inputs of setting the operating mode of the device are connected respectively to the first and second inputs the OR-NOT unit whose output is connected to the first input of the element AND, the second input of which is connected to the synchronous input of the device, the output of the element AND is connected to the first input of the modulo two adder, the second input of which is connected to the output of the K-flip-flop.