SU1354191A1 - Microprogram control device - Google Patents

Abstract

The invention relates to computing and can be used in controllers, channel-to-channel adapters, and control devices for interface systems of computer complexes. The aim of the invention is to improve the noise immunity of the device. To this end, the device containing the microprogram memory block 1 and the micro-register 3 has been entered using an encoder 5 of the micro-command number, a selector 6 for changing the logical state and a switch for the 7 modes of operation. 4 ill., 1 tab. (L: ate 4

Description

The invention relates to computing technology and can be used in controllers, channel-to-channel adapters and control devices for the interface systems of computer complexes.

The purpose of the invention is to improve the noise immunity of the device.

Fig. 1 shows a block diagram of the device J in Fig. 2, a selector for changing the logical state; FIG. 3 is the timing diagram of the operation of the selector of FIG. 4, the timing diagram of the initial sampling mode for the interface.

The table provides an example of the coding of the states of the microprogram memory unit and the encoder number of micro-instructions in relation to the EC interface of the computer.

The microprogram control unit (Fig. 1) contains a microprogram memory block 1 consisting of m programmable logic matrices (PLA) in which the address inputs are respectively interconnected, with the first address input of the memory block 1 being input 2-2 of the code teams.

the devices, and the outputs of the PLM of memory block G, respectively, are interconnected and with the information input of the register of 3 micro-instructions.

 The output of register 3, being the output of the device, is also connected to the input of the encoder 5 of the micro-command number, the output of which is connected to the second address input of the memory block 1.

The inputs of the logical state change selector 6 are connected to the operation input of the device, and the output of the selector 6 is connected to the first information input of the operation mode switch 7, the other information input of which is connected to a single pulse generator -8 (device synchronous input), and the output of the switch 7 connected to the synchronous input (C-input) register 3 micro-instructions, the reset input (R-input) of which is input 9 of the initial installation of the device. The control input of the switch 7 is connected to the input of the sign of the device mode

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When a reset pulse arrives at input 9, the device is reset, which can also be set by firmware. When a certain combination of signals at the output of the memory unit arrives at the input 2, a microcommand of the K-bit format is formed, which is fed to the information input of the register of 3 microcommands. In this case, the selector 6 changes the logical state, which is essentially a device for forming pulses, both on the leading and trailing edges of the input signals, when the logical level changes on one or several inputs, a single pulse is produced (Fig. 3, which from the output of the selector 6 through normally closed contacts, switch 7 enters the synchronous input of register 3 and writes into it a microcommand which is already at its information input. From the register 3 microcommand, the formed command enters and output 4 of the device, as well as: the input of the encoder 5, which converts the value of the microcommand to its number, while the output of the encoder 5 removes the signal that is sent along the feedback circuit to the second address input of the memory 1 for fixing the value of the microcommand before the formation of a new microcommand.

 When the combination of signals at the first input 2 changes, taking into account the previous microcommand (Fig. 4), a new microcommand is formed (or, if necessary, the previous microcommand is confirmed) 5 and at the output of the selector 6 a sync pulse is generated.

 4 jE - i

The selector 6 (FIG. 2) of the change in logic-writes the microinstruction to the 3. state register can be performed due to the formation of the change NOT 10 -10 and repeated elements l x

the outputs of which of the single sync pulse signal are greatly increased

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each other, are the selector inputs, and the outputs of the NOT elements and the repeaters are connected respectively to the first and second terminals of the capacitors, as well as to the inputs of the AND 13-13 elements, the outputs of which are connected to the inputs of the OR-NOT 14 element, whose output is the output of the selector 6 changes the logical state.

The control input of the switch 7 in FIG. 1 is labeled 15.

The device works in the following way.

When a reset pulse arrives at input 9, the device is reset, which can also be set by firmware. When a certain combination of signals at the output of memory 1 is input to input 2, a microcommand of the K-bit format is formed, which is fed to the information input of the register of 3 microcommands. At that, the change state selector 6, which is essentially a pulse shaping device, both on the leading and trailing edges of the input signals, when the logic level changes on one or several inputs, produces a single pulse (FIG. 3). from the output of the selector 6, through the normally closed contacts of the switch 7, enters the synchronous input of the register 3 and writes into it a micro-command that is already at its information input. From the output of the register of 3 microcommands, the generated command arrives at the output 4 of the device, as well as: the input of the encoder 5, which converts the value of the microcommand to its number, while the output of the encoder 5 removes the signal that is fed through the feedback circuit to the second address input unit 1 of memory for fixing the value of the microcommand before the formation of a new microcommand.

 When changing the combination of signals at the first input 2, taking into account the previous microcommand (Fig. 4), a new microcommand is formed (or if the previous microcommand is confirmed if necessary) 5 and at the output of the selector 6 a sync pulse is generated.

 4 jE - i

writes the microinstruction to the register 3. Due to the formation of the change

writes the microinstruction to the register 3. Due to the formation of the change

the input signal of a single sync pulse is significantly increased

system resistance, especially when asynchronous generation of signals is based on the Request-Answer principle, for example, when working with the EU-computer interface. In addition, the speed of the microprogrammed control unit is increased by the time of the mathematical expectation of the arrival of the clock from the clock generator. It is also possible for Q, in certain cases, to increase the size of input 2 by using feedback circuits.

The new value of the microcommand is encoded with the help of the encoder 5, which can be executed on a programmable permanent memory, and is fed to the second address input of the memory block 1. Since memory block 1 is made on a PLA, at certain values of micro-instructions, it is possible to independently operate the firmware control device from the feedback signals from the encoder 5, by excluding the logical variable from a certain conjunction of the PLA by the second group of address inputs .

In addition, the use of the PLA makes it possible to edit the firmware by writing logical units to the PLM disjunctors at a certain value of the input variable and new

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records of this value and free conjunctor.

Claims (1)

Invention Formula A microprogramming control device containing a microprogram memory block and a microinstructions register, whose information input is connected to an output of a microprogram memory block, the first address input of which is connected to an input of the device command code, characterized in that it contains an encoder for microprogram number , a logic state change selector and a mode switch, the first and second information inputs, the control input and output of which are connected respectively to the output the selector of changing the logic state, the synchronous input and the input of the device mode indication and the synchronous input of the microcommand register, the reset input and output of which are connected to the initial installation input and the device output, the input and output of the microcommand number encoder are connected to the output of the microinstruction register and the second address memory block microprograms, and the inputs of the logic state change selector are connected to the input of the operation of the device. Note, Opt.-feedback signal (Acknowledgment — Acknowledgment Signal is a sign of a command or data) Allow. before - signal time after the arrival of the sync pulse. The remaining signals (bus)