SU679980A1 - Microprogram control unit - Google Patents

Description

54) FIRMWARE DEVICE

The invention relates to the field of computer technology, in particular to the ycTpoftcTBciM of microprogramming, and can be used in data processing systems.

A firmware control device containing memory blocks, two condition check blocks, two AND elements, address registers and blocking triggers 1 is known.

The drawbacks of the device are low speed and increased equipment costs.

The closest to the invention in technical essence and the achieved result is a firmware control device containing two memory blocks, two address registers, two switches, two elements And a trigger, with the output of each switch connected to the first input of the corresponding address register, the first and second the inputs of each memory block are connected to the outputs of the corresponding address register and the AND element, each input of the device is connected to the first inputs of one AND element and the other switch 2,

The disadvantages of such a device - the complexity and low speed. The complexity of the device is due to

using in it two triggers with countable inputs. The low speed of the device is also associated with the use of triggers with a counting input, as well as with the need to make the transition from an odd (even) microcommand to an odd (even) address of the next microcommand read from one memory block, write to another register and then, through another x, the switch is written into the register of the error corresponding to the block from which this micro-command was read. At the same time, the half-cycle of following the clock pulses at each input of the device cannot exceed the value of t ,, determined by the following alignment;

.

where Sed is the read time in block

memory;

Claims (2)

 the time of writing the microcommand address to the address register; TC is the switch response time. The frequency of arrival of clock pulses 7 to each of the device inputs cannot exceed the value f J defined by the following expression: o. ji T1 2T, Thus, the need to write the address code of the next microcommand first to one address register and then rewrite it through the switch to another address register and, moreover, use triggers with a counting input that have a lower speed than a trigger with separate input, significantly reduces the speed of such a device. The purpose of the invention is to increase the speed and simplify the device. The goal is achieved by the fact that the first and second outputs of the trigger are connected to the second, respectively, first and second elements, the first outputs of the first and second memory blocks are connected to the first inputs of the second and first switches, the second outputs of the first and second memory blocks are connected respectively to the second inputs of the second and first switches and the corresponding trigger inputs, and the second outputs of the first and second switches are connected to the second inputs of the first and second address registers. The block diagram of the device shown in the drawing. The firmware control device contains trigger 1, switches 2, 3, address registers 4, 5, elements 6, 7, memory blocks 8, 9, inputs 10, 11. The first, and 12, 13, and 14, 15 second outputs of the memory blocks. The device works as follows. The trigger 1 controls the operation of the device. If it finds c in the one (zero) state, the element AND 6 (7) is opened and the reading of the information from the memory block 8 (9) by the clock pulse arriving at the input 10 (11) is allowed. Suppose that in the initial state the trigger 1 is in the single (zero) state, and on register 4 (5) there is the address of the microcommand to be read. Since element (7) 6 is open, the first clock pulse coming from the input of the device 10 (11) to the first input of the element 6 (7) reads the microcommand from the memory block .8 (9). Further, the device can operate in two modes. The first mode corresponds to the alternation of even (odd) and odd (even microcommands, the second mode realizes transitions from odd (even) to odd (even) microcommands. When the device operates in the first mode from the second output 14 (15) of memory block 8 ( 9) each time a single signal is read that goes to the zero (single) input of the trigger 1 and translates it to the zero (single) state in which the element And 7 (6) is open. Simultaneously from the first output 12 (13) of the memory block 8 (9) the address of the next micro-command is fed to the first input switch 3 (2), the second input of which receives a signal from output 14 (15) of memory 8 (9), the presence of which determines the entry of the microcommand address from the first output of switch 3 (2) through the first input to address register 5 (4 Further, the operation of the device is repeated as described above. In the second mode, the device operates as follows, there is no ria to the second output 14 (15) of the memory block 8 (9). Therefore, the trigger 1 remains in the single (zero) state, in which open element AND 6 (7). At the same time, from the first output 12 (13) of the memory block 8 (9), the address of the next microcommand goes to the first input of the switch 3 (4). The absence of a signal at the second input of the switch 3 (4) predetermines the entry of the microcommand address from the second output of the switch 3 (2) through the second input to the address register 4 (5). With the arrival of a clock pulse at input 11, a microinstruction is read from memory block 8 (9). If after this readable micro-command it is necessary to re-implement the second mode, then the process repeats as described. The half-cycle of the following clock pulses G through the device input does not exceed the value with 2 defined by the following expression: 2 MF L - Frequency of receipt of clock pulses fJ to each of the device inputs cannot exceed the value of f y g defined by the following expression:. T2 (C-, Using a new trigger element with separate inputs allows you to simplify the device as compared with a known device. Connecting a single trigger input to the output of one memory block, zero to the output of another memory block, zero output to the input of one AND element and a single to the input of another element And allows you to use a trigger to control the operation of the device. Since the trigger with separate inputs has a higher speed than the trigger with a counting input, the introduction to the circuit trigger with separate inputs increases the speed of the device as a whole. Connecting the second output of each memory block to the second input of the other switch allows you to determine the direction of the address of the next microcommand from the memory block output (to the corresponding or different address register). Connect the first output of each block The memory to the first input of another switch is designed to transfer the address code of the next micro command to the switch. Connecting the second output of each switch to the second input of other registers allows you to write the address of the next microcommand from the switch output to another address register. Thus, the introduction of these links allows to increase the speed of the device in comparison with the known device by recording the address of the next microcommand from the output of the memory unit through the switch directly to the desired address register (the one from which it should be read in the next clock cycle) Mine rewrite from one register to another. The invention The MHKponporpaftMHoro control device contains two blocks of packets, two address registers, two MytaTopa modules, two AND elements and a trigger, with the output of each switch connected to the first input of the corresponding address register, the first and second inputs of each memory block are connected to the outputs of the corresponding register address and element And, the first input of the device is connected to the first inputs of the first element And the second switch, the second input of the device is connected to the first inputs of the second element And the first switch, I distinguish Not only that, in order to increase speed and simplify the device, the first and second outputs of the trigger are connected to the second inputs of the first and second elements, respectively, the first outputs of the first and second memory blocks are connected to the first inputs of the second and first switches, the second outputs of the first and the second memory blocks are connected respectively to the second inputs of the second and first switches and to the corresponding inputs of the trigger, and the second outputs of the first and second switches are connected to the second inputs of the second and first switches address registers, respectively. Sources of information taken into account during the examination 1. USSR author's certificate 437072, cl. G 06 F 9/12, 1972. 2. Authors. Certificate of the USSR 451080, cl. G 06 F 9/12, 19-74 (prototype). 11 -I 15