SU653747A2

SU653747A2 - Binary counter

Info

Publication number: SU653747A2
Application number: SU762424199A
Authority: SU
Inventors: Владимир Алексеевич Грехнев; Виктор Александрович Шлыков
Original assignee: Предприятие П/Я В-2097
Priority date: 1976-12-03
Filing date: 1976-12-03
Publication date: 1979-03-25

Description

Изобретение отноомтс к автоматике и вычислительной технике и может быть исполыювано в устройствах измерени временных интервалов, а также в устройствах оиреле .юии координат.The invention relates to automation and computer technology and can be used in devices for measuring time intervals, as well as in electronic devices of coordinates.

В основном авт. св. Хй 418982 онисано устройство, содержан1ее четыре разр да, каждый из которых содержит триггер пам ти , ком.мутациоиный триггер и элемент И-НЕ, причем единичный выход триггера нам ти соединен с единичным входом коммутационного триггера, единичный выход которого соединен с входом элемента И-НЕ, а нулевой выход соединен с едикичным входом триггера пам ти данного разр да, с нулевыми входами коммутационных триггеров и триггеров пам ти всех предыдущих разр дов и с входом элемента И-НЕ предыдущего разр да, выходы элементов И-НЕ первого и второго разр дов соединены с обоими входами коммутационных триггеров соответственно второго и третьего разр дов, выход элемента И-НЕ третьего разр да соединен с нулевым входом коммутационного триггера четвертого разр да, выход элемента И-НЕ четвертого разр да соединен сBasically auth. St. Hy 418982 onisano device, containing four bits, each of which contains a memory trigger, a commutating trigger and an AND – NE element, the unit trigger output of which is connected to the unit input of a switching trigger, the unit output of which is connected to the input of the element I- NOT, and the zero output is connected to the monitored memory trigger input of this bit, to the zero inputs of the switching triggers and memory triggers of all previous bits and to the input of the AND-N element of the previous bit, the outputs of the AND-N elements of the first and second bits are connected to both inputs of switching triggers of the second and third bits, respectively; the output of the third-level AND-NO element is connected to the zero input of the fourth-level switching trigger; the output of the fourth-level AND-NE element is connected to

входом дополнительного элемента И-НЕ, выход которого соединен с входом элемента И-НЕ четвертого разр да и с нулевыми входами всех триггеров пам ти и коммутационных триггеров делител 1. Однако известное устройство недостаточно надежно.the input of an additional NAND element, the output of which is connected to the input of the NAND element of the fourth bit and with zero inputs of all memory triggers and switching triggers of divider 1. However, the known device is not reliable enough.

Цель изобретени - повышение надежности устройства в работе.The purpose of the invention is to increase the reliability of the device in operation.

Это достигаетс тем, что в двоичном счетчике , содержащем четыре разр да, каждый из которых содержит триггер пам ти, коммутационный триггер и элемент И - НЕ, выход элемента И-НЕ второго разр да подключен к единичному входу коммутационного триггера четвертого разр да.This is achieved by the fact that in a binary counter containing four bits, each of which contains a memory trigger, a switching trigger and an AND-NOT element, the output of the second-digit AND-NOT element is connected to the single input of the fourth-digit switching trigger.

На чертеже изображена структурна электрическа схема двоичного счетчика.The drawing shows a structural electrical circuit of a binary counter.

Claims

The binary counter contains the 1 signal tina 1, the elements AND-NOT 2-5 cootBeTCTBCHHo of the first to fourth bits, the additional element AND — NOT 6, the elements AND-NOT 7-14, which in pairs form the switching triggers of the corresponding first and fourth bits, the elements AND - NOT 15-22, which in pairs form memory triggers, respectively, of the first and fourth bits. The device works as follows. In the initial state, all memory triggers are in the zero state, and the clocking signal arriving at bus 1 is absent (equal to logical zero). In this case, at the outputs of the AND-NE elements 2, 3, 4, 5, 15, 17, 19, 21 is a logical zero, at the outputs of the remaining AND-NOT elements there is a logical one, therefore, with the arrival of the first clock pulse, only the AND element NOT 8, set the first-bit memory trigger to one. At the end of the clocking pulse, a logical unit appears at the output of the NAND 2 element. With the arrival of the next clock signal, the AND-NOT 10 element is triggered, the second-bit memory trigger is set to one, and the first-bit memory trigger is set to zero. In order to prevent the NAND element 8 from operating at the time of the clocking signal, after the first bit memory trigger is set to zero, and also to ensure stable operation of the NANDI element 10, the output of this element is connected to the inputs of the AND elements. NOT 2, 8, 9. With the arrival of the third clock pulse, only the AND-NE 8 element is triggered, since the outputs of the AND-NOT 2-5 elements are logical zeros. After the clocking pulse expires, a logical unit appears at the output of the NAND-2 element, and since the second-bit memory trigger is in the one state, the logical unit also appears at the output of the IS-NE element 3. It is obvious that the AND-HE elements 4, 11, 3, 9, 2, 7 work as a half-adder, folding the transfer units into a discharge with the state of the memory trigger of the discharge, and the signal at the outputs of the AND-HE elements 2-5 can change only after the end of the tactical impulse. Thus, with the arrival of the fourth tactical impulse, the NAND 12 element is triggered, the third-bit memory trigger is set to one, and the low-order memory triggers are set to zero. The presence of a connection from the output of the element AND-NO 12 to the inputs of the elements AND-NO 3, 8, 10, 11 again prevents the counter from operating incorrectly. Similarly, the AND-NO 14 element is triggered only when the fourth-bit memory trigger is at zero and the output of the AND-NO 4 element is a logical one (this means that the memory triggers of the previous low-order bits are one). The signal equal to logical zero, which appears at the output of the NAND 14 element, sets the fourth-bit memory trigger to one, and the low-order memory triggers to zero. Then the counting continues in the same way until after the arrival of the eleventh clocking pulse the code 1011 is set in the divider. At the same time, a logical unit appears at the output of the IS-NOT 3 element, therefore the output of the IS-NOT element 13 appears and the output of element 5 is a logical one. Therefore, with the arrival of the twelfth clocking pulse, an additional element IS-NOT 6 is triggered, setting the pulse counter to its initial state. The invention of the binary counter on the author. St. No. 418982, characterized in that, in order to increase the reliability of the device in operation, the output of the second stage NAND cell is connected to the single input of the fourth trigger switching trigger. Sources of information taken into account in the examination 1. USSR author's certificate № 418982, cl. H 03 K 23/02, 1972.