SU1497743A1 - Fibonacci p-code counter - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to expand the functionality due to the operation of the device in two code modifications of P-Fibonacci codes. The scaling circuit contains triggers, AND elements, OR elements, NOT elements, and NAND elements. With the external signal "Logic zero", the transfer device operates on the control input in the 1-Fibonacci code. With an external "Logic unit" signal, the scaling circuit operates in a 2 Fibonacci code on the control input. The reset trigger triggers are reset to the initial state by applying a low potential to the installation input. The counting signal arriving at the counting input changes the state of the triggers of the scaling circuit in accordance with the signals present at its and K-inputs at the previous time. 4 ill., 2 tab.

Description

The invention relates to computing and can be used in the construction of scaled units of digital computing devices.

The aim of the invention is to extend the functionality of the view control code view.

Figure 1 shows the electrical circuit diagram of the scaler; FIG. 2 shows a fuctional operation. —the flap diagram of the connection of two enumerators in the Fibonacci p-code; on fig.Z - timing diagram of the device when figure 4 is the same at.

The scaling device in the Fibonacci p-code (Fig. 1) contains 1K-triggers 1-3, elements AND 4-7, element OR 8, elements NOT 9-12, elements AND NOT 13-15, elements 16 and 17, the element OR 18, the elements AND 19, 20 and the element AND-NOT 21.

The forward outputs of the flip-flops are informational outputs 22-24 of the counting device (FIG. 2), the inverse output of the trigger 1 is the control output 25, the output of the HE element 9 is the transfer output 26. The input 27 is the counting input of the counting device and is connected to the inputs synchronization triggers 1-3 and the first inputs of the elements And 4-7. Input 28 is a reset input and is connected to the R inputs of the flip-flops 1-3. Input 29, which is the first control input, is connected to

NU

)

four

WITH

3

input is input element 10, NOT with the first and second inputs of elements AND 19 and 20, respectively, and with the third input of element AND 4. Input 30 is the second control input connected to the input of element NE 1 1, and the first input of the element AND -NOT 15 and the second input element AND 7. Input 31 is an input of the mode and is connected to the input of the element NO 12, the first inputs of the elements AND-NOT 13 and 14, the second input of the element AND-NOT 15 and the first and the third inputs of the elements 17, 6 and 7, respectively. The direct trigger output is connected to the first 1-input of trigger 2, the second input of the element 16 and the fourth input of the element 6, the inverse output of trigger 1 is connected to the third K-input of trigger 2, the third input of the element 17 and the first inputs of the elements 20 and NAND 21. The forward output of trigger 2 is connected to the first 1 input of trigger 3, the fourth and third inputs of the And 7 and 5 elements, respectively. The inverse output of the trigger 2 is connected to the second output K of the trigger 3, the second input of the element I 19 and the combined second and third I - and K-in ;; trigger 1. The direct output of trigger 3 is connected to the second inputs of the AND 4 and NAND 13 elements. The inverse output of the trigger 3 is connected to the third I and the first K-inputs of the trigger 2, The outputs of the AND elements 4-7 are connected to the corresponding inputs of the element OR 8, the output of which is connected to the input of the element NOT 9. The output of the element NOT 10 is connected to the second input of the element AND-NOT 14, the second and third inputs of the elements AND 5.6, respectively. The output of the element NE is connected to the second input of the element AND 17. The output of the element NOT 12 is connected to the first and fourth inputs of the elements 16 and 5 with the corresponding, as well as to the second input of the element AND-NOT 21. The output of the element AND-NOT 13 is connected to the first I- and K-inputs of the trigger 1, the output of the element AND-NOT 1 4 - to the third I- and K-inputs of the trigger 2. The output of the element AND-15 15 is connected to the third 1-input of the trigger 3. The outputs of the elements 16 and 17 connected to the corresponding inputs of the element OR 18, the output of which is connected to the first input of the trigger 3, the second 1-input of which is connected to the output of the ment And 20, and the third K-input is connected to you

I4977A3

the course of the element And 19. The output of the element AND-NO 21 is connected to the fourth input of the element And 4.

The operation of the device will be shown using the example of organizing a six-bit scaling circuit (Figures 1 and 2) with bits 1,2,3,5,8,13 with and 1,2, 3,4,6,9 with,

In the initial state, by applying a low potential signal at the input 28, the triggers 1–3 of the counting devices are set to the zero state by their R inputs. At the outputs of the scaling devices, the state is 000 000. At each subsequent instant of time, the states of the triggers are determined by the signals present at their I- and K-inputs at the previous moment of the trigger. & In general, the signals at the I and K inputs are determined based on the following logical equations:

7 QiQjAR;

(one)

it KI QiQjR; I

Q, Q, R;

K Q.QjAR; K j Q A (Q, BP-t-Q, R),

(2)

where A, B are control signals at inputs 29 and 30, respectively; R is the mode signal at the input. The transfer signal at the output 26 of the scaler is determined based on the following logic equation:

G (AQ,) R + AQtR + + Q, AQ, R X,

where X is the input signal 27.

When a logical 1 signal is applied to the input of the element NO 12 at the input 31, the counting device operates in 2 Fibonacci code (). In this case, equations (1) and (2) take the form:

1 K, QiQj; Ii

1h

Ka QiQjA; CQ Q, AQ, B .;

G (AQ, + QjA) X

The signal of the logical element NO 12 blocks the elements AND 16, 5, At the output of the element AND-NOT 21, there is also a signal of logical 1, which arrives at the fourth input of the element AND 4.

Before the arrival of the first counting signal at the inputs I and K of the flip-flops, as well as at the control inputs 29 and 30, we have the following signals: at input 29 - the signal of logical 1, at input 30 - the signal of logical at the first

(3)

(4) exit

The I and K inputs of the trigger 1 are a logical 1 signal from the output of the AND-NOT 3 element, so on its second pass there is a logical O signal from the direct output of the trigger 3; on the second and third I and K inputs of the trigger, I is a logical 1 signal from the inverse output of trigger 2. Thus, the I trigger is in the counting mode.

On the first 1-input of trigger 2 there is a logical signal O from the direct output of trigger 1, on the first K-input there is a signal of logical 1 from the inverse output of trigger 3, on the Second K-input there is a logical signal from the input of the AND-14 element , as at its second input - the signal is log 20

At the third K input of the trigger 2, the signal is a logical 1 from the inverse output of the trigger 1. Thus, the trigger 2 is in recording mode zero.

On the first 1-input of the trigger 3 when 25, hera 1 there is a logical signal O from the direct trigger of the trigger 2, on the first K-input of the trigger 3 - a signal of logical I from the output of the element

15 Before the arrival of the fourth counting signal, conditions are formed for generating the transfer signal according to equation (4): At the second input of the element, AND A is the logical 1 signal from the trigger 3 output, and the third is from the logical I signal from the 29 input. logical I from the output of the NAND 21 element. Before the arrival of the fourth counting signal, triga 2 are in zero storage mode with logic on their I and K inputs, trigger 3 is in zero recording mode.

caused by the presence of signals from the LPI 18 signal, since at its second input 1 at its K-inputs (at the first 1 at the output of the K-input at the output of

OR 18, on the second - from the inverse output of the trigger 2, and on the third - from the output of the element (19). At inputs of element 35, there are signals of logical 1 from the output of the element HE I1, input 31 and the inverse output of trigger 1, therefore, at the output of the element 17, there is also a signal of the logical signal 17 and

The first counting signal arriving at input 27 changes the state of only the first trigger. The pa outputs of the recalculated devices are set to code 000 001 (see table 2 and figs. 3, Q).

Before the arrival of the second counting signal at the 1 inputs of trigger 2, we have logical I signals from the outputs of trigger 1,. the element AND 14 and the inverse output of the trigger 3, Thus, the trigger 2 is in the counting mode. Trigger 1 is also in the counting mode, since its signals did not change at its I and K inputs.

The second counting signal records in the counting device code 000 010 (see, table 2 and fig.Z, Q),

Before the arrival of the third counting signal, trigger 1 is in the storage mode, due to the logical signal O from the inverse output

40 koi |, which at the second input of the element OR 18 enters the first K-input of the trigger 3,

The fourth counting signal sets the first scaler to its initial state. The same signal through the elements AND 4, OR 8 and HE 9 is fed to the counting input of the next counting device (Figures 1 and 2), cQ while the state of the triggers of this counting device is similar to the state of the triggers in the first cycle. Thus, the code 001 000 is set on the recalculated devices.

0

5, Hera 1

unit 1Ы, due to the presence of a logical 1 np its 1-inputs from the direct output of trigger 2 from the output of the element I-IG 15 i pykhodl e. H 20, because (its inputs present signals of logical 1 from input 29 and inverse output of trigger 1, and on the second K-Bxo; ie, trigger 3, there is a logical O from inertial trigger of trigger 2.

The third counting signal records the code 000 100 in scaling devices (table 2, fig.Z.r.).

5 Before the arrival of the fourth counting signal, conditions are formed for generating the transfer signal according to equation (4): At the second input of the element, AND A is the logical 1 signal from the output of trigger 3, and the third from the logical I signal from the input 29. At the fourth input, there is also logical I from the output of the NAND 21 element. Before the arrival of the fourth counting signal, triga 2 are in zero storage mode with logic on their I and K inputs, trigger 3 is in zero recording mode.

40 koi |, which at the second input of the element OR 18 enters the first K-input of the trigger 3,

The fourth counting signal sets the first scaler to its initial state. The same signal through the elements AND 4, OR 8 and HE 9 is fed to the counting input of the next counting device (Figures 1 and 2), cQ while the state of the triggers of this counting device is similar to the state of the triggers in the first cycle. Thus, the code 001 000 is set on the recalculated devices.

trigger 2, trigger 2 - in the mode for -, - s (see, table 2, fig.Z, Q4). On the zero zero, because on its Pervm 25, connected to the inverse output1-input, the logical O signal, the hell of the trigger 1 of the second recalculated

On the K-inputs signals of logical 1; device, set the signal

trigger 3 is in Recordogogic O mode, which at input 29

enters the first recalculated device (figure 2).

In the next cycle, the trigger states correspond to those described above. The fifth counting signal sets the code 001 001. Before the sixth counting signal arrives, a condition is created for transferring the counting signal from AND 6, the second, third and fourth inputs of which contain the signals of logical 1 from input 31, the output of HE 10 and direct trigger output 1, respectively. Triggers 2 and 3 of the first recalculating device are in the storage modes caused by the signals of the logical O from the outputs of the AND-14, AND 19 and And 20 elements, respectively. The trigger 1 of the first scaler is in the counting mode, due to the logical I signals at its I- and K-inputs from the outputs of the AND-NE 13 and inverse output of the trigger 2 o

The sixth counting signal records the code 000 in the first counting device, i.e. brings it back to its original state. At the same time, the same signal, output through the elements AND 6, 11PI 8 and HE 9, is fed to the counting input of the second counting device on input 27. The triggers of the second counting device are in modes similar to the second cycle of operation of the first counting device.

The sixth counting signal records the first device code 010 000

In addition, the work of recalculating devices is similar to the previous cycles with tsn only the difference that the transfer signal in the ninth cycle to the first input of the element OR 8 comes from the output of the element And 7, the second and fourth voods of which contain signals of logical 1 from the output of the trigger 2 and the input 30 of the first counting device.

Before using the last (thirteenth) counting signal in scaling devices, the code 100 100 appears, i.e. The triggers of the scaling devices are in modes similar to the modes of the third cycle of operation of the first scaling device. Thus, the thirteenth counting signal brings recalculators to the initial state of 000 OOP.

5 0 5

ABOUT

Q q

Q

five

When a logical O signal is applied to the input 31, the conversion units are transferred to the counting mode in the 1 Fibonacci code, and the logical O signal from input 31 blocks the NAND unit 13. After this, the trigger states are determined by the signal from the inverse output of the trigger 2. Similarly, the element AND-NRE 14 is blocked and the state of the trigger 2 is determined by the signal from the direct output of the trigger 1 and the signal from the inverse output of the trigger 3. The signal from input 31 also blocks the elements AND 17, AND-HE 15, 7 and AND 6.

The state of the triggers of the scaling devices and the condition of the return of the transfer signal are determined on the basis of equations (1) and (2) for the case of R 0.

ii Ki I, - Q.Oj; 1h

Cg Q, Qj; Kj, carry signal

G (AQa + QiQ, A) X. one

In this mode, the operation of the device

Table 1 and the timing diagram of FIG. 4.

Thus, counting in two code modifications of the Fibonacci p-codes, i.e. expands the area M); device names.

Claims (1)

Invention Formula The scaling device in the Fibonacci p-code, containing the first, second and third triggers, the reset inputs of which are connected and connected to the reset input of the counting device, the direct outputs of the triggers are information outputs of the counting device, the counting input of which is connected to the synchronization inputs of all the triggers. and the first inputs of the first and second elements AND, the outputs of which are respectively connected to the first and second inputs of the OR element, the output of which is connected to the input of the first element NOT, the output of which is the transfer output of the scaler, the first control input of which is connected to the third input of the first element AND and the input of the second element NOT, the output of which is connected to the second input of the second element AND, the third input of which is connected to the first 1 input of the third trigger and direct the output of the second trigger, the inverse output of which is connected to the second K-input of the third trigger and with the combined second and third I- and K-inputs of the first trigger, the direct output of which is connected to the first 1-input of the second trigger, the third K-input which is connected to the inverse output of the first trigger, which is the control output of the counting device, the third 1 input and the first K input of the second trigger are combined and connected to the inverse output of the third trigger, the forward output of which is connected to the second input of the first element And, characterized in that, in order to extend the functionality by providing control of the type of code, the third, fourth, fifth, sixth, seventh and eighth elements are entered into it AND, the third and fourth elements are NOT, the first, second, third and fourth elements NAND and the second element OR, whose approach is connected to the fourth than the direct output of the first trigger is connected to the second input of the fifth element AND and the fourth input of the third element AND, the third input of which is connected to the second input of the second element AND, with the output of the second element NOT and the second input of the second element NAND, the first input of which is connected to the input of the mode of the counting device, to the first input of the first NAND element, the second input of the third NAND element, the fourth element input, the second input of the third element AND, the third input of the fourth element Inc to the first input of the sixth element AND, whose third input is connected to the first input of the eighth element AND, to the first input of the fourth element NAND, with the inverse output of the first trigger, the first control input of the counting device is connected to the first and second inputs of the seventh and eighth elements AND, the second output of the second trigger is connected With the fourth input of the fourth element I, the second input of which is connected to the first input of the third element NAND, to the input of the third element NOT and is the second control input of the counting device, the counting input is The first is connected to the first inputs of the third and fourth elements AND, the outputs of which are connected respectively to the third and fourth passes of the first element OR, the inverse output of the second trigger is connected to the second input of the seventh element AND, the output of which is connected to the third K-input of the third trigger, the first K - the input of which is connected to the output of the second element, the inputs of which are connected respectively to the first and sixth elements of the I, the direct output of the third trigger is connected to the second input of the first NAND element, the output of the cat pogo is connected to the first I and K inputs of the first trigger, the output of the second element is NOT connected to the second I and K inputs of the second trigger, the output of the third element is NOT connected to the second input of the sixth element, and the output of the fourth element is NOT connected to the first to the input of the fifth element AND, to the fourth input of the second element AND, to the second input of the fourth element NAND, you the input of the first element is And, the output of the eighth element And is connected to the second 1-input of the third trigger, the third 1-input of which is connected to the input of the third AND-NOT element. Table 1 table 2 Sifod 28 vzhod 27 ri & l Compiled by O. Skvortsov Editor A.Makovska Tehred A.Kravchuk Proofreader I.Gorn Order 4456/55 Circulation 884 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Subscription