SU991405A1 - Data output device - Google Patents

Description

one

Isofeating is intended for use in devices of digital computing technology for accumulating and outputting information to an external device, in particular, for accumulating and outputting telemetry information on the performance of nodes of computing devices.

Known devices for data input contain a buffer register, the inputs of which are the inputs of the device, the output register, the output of which 51. Output outputs, devices and circuits that provide a copy of information from the buffer register to the output register, output to the external registers and device registers. C1.

The drawbacks of the device are its complexity and low quality. work due to loss of information.

The closest in technical dryness to the present invention is a device for outputting information, containing

the buffer memory, the outputs of which are connected to the shift register, the outputs of the shift register are connected to the inputs of the group of elements AND whose outputs are connected to the inputs of the link node whose outputs are the outputs of ycTpoifcTBa, the first, second and third elements of AND, memory Control and clock generator, where the control console information input is the input of the device, the outputs. the memory of control is connected to the first inputs of the first, second and third elements AND, the control input of the shift register - and the second inputs of the group of elements AND; the arcs of the sync pulse generator are connected to the second Ecode, BToptTro and the third elements AND, the outputs of which are connected to the control the inputs of the buffer memory, the shift register in the control memory 12.

Claims (2)

The disadvantage of the device is the no-f ter input information 39 coming into the memory during the processing of the S1I information, i.e. during the census of the buffer memory information 43 into the shift register and preparing the 6jTl3epHofl memory for receiving new information. In addition, the presence of the driver time (control memory) and the driver of the shear conditioner significantly complicates the device circuitry and increases the hardware costs. The circuit of the invention is the simplification of the device. The goal is achieved by the fact that the device for outputting information contains the first register, whose 5 inputs are kgg with information inputs of the device, a group of AND-NOT elements, the second register whose D and K inputs are connected to the. D inputs of the first register and are the first input of the device, the element AND-NOT, the first input of which is connected to the output of the second register and is the first output of the device and the input of the element AND-NOT enters the second output of the device, the element OR, the element OR is NOT the trigger and the third register are entered , D - whose codes connected to the outputs of the first register, and the outputs - to the corresponding D-inputs of the second register and to the first inputs of the elements of the NAND group, the second inputs of the elements. AND-NOT groups are connected to 5-INPUT of the trigger, the first input of the element OR-NOT and are the second input of the device, the outputs of the elements of the IS-NOT group are connected to the C-inputs of the corresponding bits of the first register, the R-inputs of the first register are connected to R is the input of the second register, the first input of the OR element and is the Device Input, the second input of the OR element is connected to the second inputs of the AND-NOT group elements and OR-NOT and is the fourth input of the device, the output of the OR element is NOT connected to the C-input the second register, the output element OR is connected to the R input a trigger whose output is connected to the C-inputs of the third register and the control input of the second register. On f1pg. 1 shows a functional diagram of the device; 2, time diagrams of the device operation. The device for outputting information contains the first register 1, the second register. 2, the group of elements AND-NO 3, the third register 4, the element AND-NO 5, the element OR 6, the trigger 7, the element OR-NOT 8, the input 9 Request, input 10 Installation 5 input 11 Clock pulse (TI), O stroke 12 - zero potential bus, output 13 - first output, output 14 second output. The device works as follows. The information enters the 5 inputs of register 1 triggers, is remembered and simultaneously arrives at the D inputs of register 2 triggers. By request, trigger 7 is set to one, the information on register 2 triggers is fixed, and register 4 is switched to parallel operation . The falling edge of the inverted signal. The request is made by copying information from all bits of register 2 into register 4. Trigger 7 is set to zero state by TI signals and register 2 is triggered and register 4 is switched to sequential mode of operation. On the rising edge of the inverted TI signals, the information is output by the register 4 by a serial code to the first output of the device in the form of voltage levels or in the form of pulses gated by TI signals on the NAND 5. Element . If there is information at the output of a register bit 2 by a signal. A request at the output of the NAND element from group 3 forms a pulse signal which, with a falling edge, sets the corresponding register buffer register 1. If there is no information in register bit 2, the setup signal In O, the corresponding bit of register 1 is not generated and, thus, the information received in buffer register 1 during the census in register 4 is saved for further processing in the device. Introduction to the device of new units allows creating an output device that operates without loss of input information, and also does not require additional synchronizing signals or pulse distributors for its operation, which greatly simplifies the device. Formula of the invented Device for outputting information containing the first register, 3-inputs of which are device information pairs, group AND-NOT element of the second register, 3 and K-inputs of which are connected to the D-inputs of the first register in -NON, the first of which is connected to the output of the second register and is the first output of the device, and the output of the AND-NOT element is the output output of the device, characterized in that, in order to improve the device, the OR element, trigger and tert are entered into it th register, D-inputs of which are connected to the outputs of the first register, and outputs to the corresponding D-inputs of the second register and to the first inputs of the NAND group elements, the second inputs of the NAND group elements are connected to the S input of the trigger, the first input of the OR element -NON W is the second input of the device, the outputs of elements 9 56 AND-NOT groups are connected to the C-codes of the corresponding bits of the first register, R-inputs of the first register are connected to the I-input of the register, the first input of the OR element and are the third input of the device the second input element OR. connected to the second inputs of the AND-HH group and OR-NOT elements and is the fourth input of the device, the output of the OR-NOT element is connected to the C input of the second jierHCTpa, you-; the stroke of the OR element is connected to the R trigger, the output of which is connected to the O-inputs of the third register and the control, the input of the second register. Sources of information taken into account in the examination 1.Auttofsky certificate of the USSR No. 651336, cl. Q 06 F 3/04, 1979. 2. USSR author's certificate; No. 773613, cl. G About F 3 / О4 „198О (prototype). ia four II  "J “- well MV C "PC “U P“ e e