SU1478193A1 - Reprogrammable microprogrammer - Google Patents

Abstract

The invention relates to automation and computing and can be used to control various devices, including external devices of computer systems. The purpose of the invention is to expand the field of application by simulating a sequence of control signals in any combination. The reprogrammable device for firmware control contains registers 1,2, decoder 4, N first registers 5, second element AND 6, pulse generator 7, N first elements AND 8, element OR 9, block 12 of reprogrammable microinstructions memory, N first triggers 13, the first 10 and second 11 pulse counters, trigger 3. This device allows you to simulate a sequence of control signals in any combination. 3 il.

Description

.and

na

four

four

00

CO 00

The invention relates to automation and computing and can be used to control various devices, including external devices of computer systems.

The purpose of the invention is to expand the field of application by simulating a sequence of control signals in any combination.

Fig. „1 is a block diagram of a reprogrammable device for firmware control; in fig. 2 shows an example of a control microprogram and a timing diagram of control signals; in fig. 3 is an example of a counter solution.

The reprogrammable device for firmware control (Fig. 1) contains the second 1 and third 2 registers, the second 3 trigger, the decoder 4, the first first registers 5, the second element AND 6, the generator 7 pulses, the first elements AND 8, the element OR 9, the first 10 and second 11 counters pulse-in, block 12 of the reprogrammable memory of micro-commands, n first triggers 13, input buses, enable-write entries 14, read permission 15, information input 16 of the second register 1, input 17 of the element 6, information input 18, third register 2, inputs 19 ,, - 19.4 resolution and, informational inputs 20, - -Ohm first registers 5, outputs 21.2,23, - 23t first triggers 13 and output 24 of register 1 „

In Fig. 1, the following notation is accepted: Q - information output, D - information input, RFP - write enable input, THU - read enable input, S - set unit input, R - set zero input, A - address input, $ - enable entry

The delay counter 10 consists of a signal generator 25, a high-frequency generator 26 of clock signals and a counter 27 (FIG. 3).

The device works as follows.

Preliminarily, in the first registers n 5, the starting addresses (reduced by 1) of the microprograms corresponding to the external device control commands are recorded sequentially according to the enabling signals 19, -19P and the inputs 20, -20P.

flashes in the microinstructions reprogrammable memory block. Input 14 is given a signal allowing the second register 1 to write the address of the device under control to input 16, and the command code to the third register 2 to input 180 The command code is decrypted in the decoder 4 and the enabling signal from the output decoder 4 is fed to one of the n first elements And, through which the starting address minus one sequence of microinstructions (previously written in one of the first registers 5) passes to the input of the second counter 11 pulses and the signal from you ode elements onto OR 9 is recorded in the second counter 11 pulses.

According to the read permission signal 15, the address of the device under control is output 24 to the communication channel with the control devices. A device with the specified address responds about the readiness (signal 17) of receiving control signals 21–23gps of the outputs of flip-flops 13 or data series 24 from the register 1 output. The second input of the second element And 6 starts the generator of 7 clock pulses. The clock pulses arrive at the incremental input. the second counter 11 pulses and through the first counter 10 delays to the input of the read resolution of the block 12 of the reprogrammable memory

When a signal arrives at the input D of the pulse counter 10, a high-frequency generator 26 is started, the counter 27 counts the pulse train, and from the counter output the signal is taken to the input of the driver 25, the clock signal generator 26 is generated and stops and resets the counter 27 to its initial (zero) state unit 12 of the reprogrammable microcommand memory is fed to the inputs of the first flip-flops 13 and form a sequence of control signals (Fig. 2) that are transmitted to the communication channel with the control device the command to execute the signal control command g + 2 and m + 3 resets the second trigger 3 and stops the pulse generator 7. When the signal m + 3 arrives at the input of the pulse generator 7, the latter stops, the input D of the first counter 10 pulses is not received and it is set to initial state "

Claims (1)

Invention Formula A reprogrammable firmware control device containing a pulse generator connected to the input of the first pulse counter, a second pulse counter whose output is connected to the address input of the reprogrammable memory block, the first elements I, n the first registers and the second element that, in order to expand the field of application, a descrambler, an OR element, a first flip-flop, a second flip-flop, a second and a third registers are entered into it, and the output of the third register is connected to the decoder's input, the outlets of which are connected to the permitting inputs of the corresponding first elements AND and the corresponding inputs of the element OR, the output of which is connected to the recording enable input of the second pulse counter, and the information input connected to the outputs of the group of the first elements AND, the outputs of the first registers are connected to information the inputs of the first elements And, the output of the pulse generator is connected to the incremental input of the second pulse counter, the output of the first pulse counter is connected to the enable input of the read block The programmable memory, the output of which is connected to the installation inputs to 1 and to the installation inputs in O n of the first triggers, the output of the reprogrammable memory block is connected to the read enable input of the second register, to the installation input to the second trigger, and to the first input of the pulse generator, inputs enable the recording of the second and third registers are interconnected and with the input set to 1 the second trigger, the output of which is connected to the first input of the second element And, the output of which is connected to the second input of the pulse generator, the output of the second register, the second input of the second element And the inputs n of the first triggers are the device output buses, and the write enable inputs and the second register reads, the information inputs of the first registers, the second and third registers, the write enable inputs of the first registers are the device input buses. mi п0 т + 3 1 micro 3 4 5 s 7 AT 9 ten 1f 12 13 It 15 sixteen Fig.Z