SU1619340A1 - Microprogram control device for programmer - Google Patents

Abstract

The invention relates to automation and computing technology and is intended to form time diagrams of the programmer. The purpose of the invention is to expand the functionality by flexibly managing the sequence of generated signals. The goal is achieved by introducing a logical block of signals into the device. il ",

Description

The invention relates to automation and computing, and is intended to form time diagrams by programming) (their signals from a universal programmer.

The purpose of the invention is the extension of functionality due to the flexible control of the sequence of generated signals and the simplification of the programmer

Fig, 1 shows the block diagram of the device; FIG. 2 is a functional block diagram.

The device contains a generator 1, a logical block 2, a timer 3 (programmable three-channel), a mode control register 4, an address counter 5, a memory block 6, an output register 7, inputs 8 information control recordings of the device, an output 9 of generator 1, first 10 and the second 11 timer outputs, the first output 12 of register 4, the second output 13 of register 7, first 14, second 15, third 16, fourth 17 and fifth -18 outputs of block 2,

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the second 19 output of the register 4, the third 20 output of the timer 3, the output 21 of the device „

The firmware control device works as follows.

The control computer is given a duration of 3, a duty cycle and the number of programming pulses by writing the corresponding codes to the first, second and third channels of timer 3. Then, in register 4, the starting address of the required microprogram and the timer enable bit are set. Signal from timer output 11 3, the passage through block 2 removes from the output 17 the signal of the initial installation of the counter 5 and generates at the output 16 of the block 2 a sequence of clock pulses arriving at the clock input of the counter 5, which forms the sequence of addresses for bchk 6, which provide reading into the register 7 of the control sequence for switching on the programming signals. The signal from the output 13 of the register 7 is used to control the operation of the device. At the end of the sequence g3fflSS S

31619340

signal inclusion

output 13 changes its state, prohibiting the formation of counting pulses at output 16 of block 2 The device stops at the current step, fixing the state of control signals at output 21 until the end of the pulse at output 11 of timer 3, which corresponds to the programming mode device is determined by the pulse duration at the output 11 of the timer 3 ". At the end of this pulse, the block 2 resumes the formation of the counting pulses at the output 16, ensuring the execution of the control signal activation sequence At the last step of this sequence, the signal. from output 13 is transferred to the initial state, ensuring the formation at output 17 of block 2 of the initial setting signal of counter 5, which returns the device to the initial state. Another output pulse Set the zero state of output 13 of the output register 7 prohibits the transmission of pulses from master oscillator 1 to the counting input of counter 5 of the address of microinstructions before the end of the programming pulse C.

The signal at the input of the initial installation of counter 5 prohibits modifying the address of the microcommand before the programming pulse arrives from output 11 and returns the counter 5 to the initial state after the end of this pulse and the output 13 of output register 7 is set to

Data is written from memory block 6 to output register 7 by the signal (18) generated by master oscillator 1 o

Claims (1)

Invention Formula A firmware control device for the programmer that contains a De 11 of timer 3 resumes the shape controller, the control register of the control signals at the output 21 of the device. After generating a specified number of control signals, the signal from the output 20 of timer 3 resets the output at the output 19 of the register 4, canceling with the register enable input timer 3 and stopping the mode control, second output of the boot, counter, memory block, output register, generator, the output of which is connected to the first counting input of the timer, the third output of which is connected programming process The operation of block 2 is described by the expressions: (); RESET OV2 HALT; With IN1. The zero state of output 12 of register 4 ensures that the signals from the outputs 10 and 11 of timer 3, respectively, are transmitted to the counting inputs of the second and third channels of the timer. the timer counters are connected in series. The first channel of the timer determines the duration, the second - the duty cycle and the third - the number of pulse programmers The single state of the signal from output 12 provides the connection of the counting inputs of the second and third channels of the timer to the output of the generator 1 "This mode is used when programming with single pulses. The first channel of the timer does not use c, the second determines the duration of the programming pulse, the third time of the programming pulse cycle ,, g with the enable input of the operation of the mode control register, the second output of the cobots, the counter, the memory block, the output register, the generator, the output of which is connected to the first counting input of the timer, the third output of which is connected five 0 " five five The output of the address counter is connected to the address input of the memory unit, the output of which is connected to the first information input of the output register, the first output of which is the device output, information inputs of the timer, operating mode control register and memory block The information inputs of the device, the recording control inputs of the timer information, the control register and the memory block are the recording control inputs of the device, characterized in that, in order to expand neither functionality due to flexible control of the sequence of generated signals and simplification of the programmer, a logic block is entered into it, the first input of which is connected to the generator output, the second, third inputs of the logic block are connected respectively to the first, second outputs of the timer, the fourth and fifth outputs of the logic block connected respectively with the first output of the control register and the second output of the output the register, the first and second outputs of the logic block are connected to the second and / third counting inputs of the timer, respectively, the third and fourth outputs of the logic block are connected sof1. Responsibly with the counting input and the initial setup input of the counter, the fifth output of the logic unit is connected to the second information input of the output register. 2