SU1522187A1 - Digit signal generator - Google Patents

Abstract

The invention relates to automation and computing and can be used to generate software-defined sequences of digital signals in automated control systems for issuing stimulus values in the monitoring and diagnostics of digital devices. The goal is to expand the class of problems to be solved by increasing the duration of a series of pulses at a given frequency of their following. The digital signal generator contains the master oscillator 1, the counter control start node 3, the pulse width code register 4, the trunk communication line 5, the OR 6 element, the And 7 element. The goal is achieved by introducing subtractive counters 2.9, memory block 8 , node 10 control issue address. 4 il.

Description

The invention relates to computer technology and automation for generating software-defined sequences of digital signals and can be used in automated control systems to provide stimulus values for monitoring and diagnosing digital devices in the course of their production and operation.

The purpose of the invention is to expand the class of solved problems by increasing the duration of a series of pulses at a given frequency of their following,

Figure 1 shows the functional diagram of the proposed generator; Fig. 2 is a functional diagram of a meter control start unit; FIG. 3 is a functional diagram of an address management node; 4 is a timing diagram of the operation of a digital signal generator;

The digital signal generator (Fig. 1 contains the master oscillator 1, the first subtractive counter 2, the node 3 controlling the start of the counter, register 4 of the pulse width code, trunk line 5, communication, the element OR 6, and the element 7, block 8. .pam, the second subtraction counter 9, the node .10 managing the address.

The node 3 for controlling the start of the counter contains a D-flip-flop 11, an element OR 12, an element NOT 13, an element AND 14, a node 10 controlling the address address contains First K5-three, a gun 15, element AND 16, a second RS-trigger 17, an element NOT 18, element and 19.

The run control unit 3 of the counter (Fig. 2) contains a D-flip-flop P, designed to delay one cycle of information from the loan output of the first, subtractive counter 2, the OR 12 element, which generates a write enable signal from the register 4 of the pulse width code into the first subtractive counter 2, the element NOT 13, which inverts the control signal obtained from the output of the trunk line 5 and the element I 14, once again passes the reference frequency of the master oscillator 1 to the counting input of the first subtractive counter 2 depending on the value of the log eskogo signal at the output of NOT circuit 13. D-latch 11 is a second input node 3 counter start control, clock input

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P-flip-flop 11 is connected to the first input of the element AND 14 and is the third input of the control start node 3 of the counter, the output of the D-flip-flop 11 is connected to the first input of the OR element 12, the second input of which is connected to the input of the HE element 13 and is the first input of the node 3 controls the start of the counter, and the output of the HE element 13 is connected to the second input of the element AND 14, the output of the element AND 14 is the first output, and the output of the element OR 12 is the second output of the node

3 run control counter.

The address issuing control unit 10 (FIG. 3) contains the first RS-flip-flop 15 necessary to generate the start of the enabling signal to the control input of the And 7 element upon the arrival of the first positive pulse from the loan output of the first subtractive counter 2 through the And 16 element, the second RS- trigger 17, designed to form the end of the enable signal at the control input of the element And 7 upon receipt of the first positive pulse from the loan output of the second subtractive counter 9, as well as the element NOT 18 and the second element And 19. The first input of the First Ele cient and 16 is a first input of the control unit 10 issuing addresses. The second input of the element 16 is connected to the output of the element 18, the input of which is the third input of the address control node 10 and connected to the input of the first short-circuit trigger 15 and the third input of the second RS-vpHrrepa 17. R-input of the second RS-trigger 17 is the second input of the node 10 of the control address address, and the RS-TpHr output 17 connects to the first input of the second And 19 element. The second input of the second And 19 element is connected to the output of the first RS flip-flop 15j on whose S input is connected element And 16, the output of the second element And 19 is the output of the node 10 control all whose addresses.

The digital signal generator works as follows

- Through the trunk line 5, information is recorded,: corresponding to the parameters of the output sequence, namely: in the register

4 codes of the pulse duration is written down a code that determines the duration of the clock pulses of the output information; in the second subtractive counter 9, a code is recorded corresponding to the cycle length of the output information; In memory block 8, the value of the output information is recorded.

Then, via the trunk line 5, a command is issued to start a programmable digital signal generator by issuing a control signal to the first input of the counter launch control unit 3, the control input of the second subtractive counter 9 and the third input of the address issuing control unit 10. At the start command, the first subtractive counter 2 starts working on the subtraction and issues a signal to exit the loan when the code at the information output of counter 2 is zero. This signal, via the control start-up unit 3, is fed to the control input of the first subtractive counter 2 and the pre-recording input code is recorded, and also fed to the counting input of the second subtractive counter 9, which sets the current address for memory block 8. When the next pulse arrives at the counting input of the second one that reads the counter 9, the digital signal generator supplies information to the following address, etc. When the second subtractive counter 9 is set to the zero position, it issues a signal Through the control node 10

addresses to install in O element And 7, i.e. end of the cycle of informa- tion.

The digital signal generator has two operating modes: the mode of recording information about the parameters of the output information, the mode of transmitting information. The recording mode is determined by the driver 1 via the trunk line 5 of the communication to the first input. The node 3 of the control for starting the counter, the third input of the node 10.

Upon receipt of the input to the node 3 of the control by starting the counter, the reference frequency is passed to the counting input to the first subtractive counter 2, and the counter 2 begins to subtract from the code recorded at the pre-recorded input b. When the first subtractive counter 2 is installed, the zero position at the output and the first subtractive counter 2 to generate a positive pulse, which, entering the control unit 3 for starting the counter, is delayed by one clock of the master oscillator 1 and fed to the input to set the first subtractive counter 2 to its original state, i.e. recording the pulse duration code 5, the first positive pulse sets the output / output of the address control node 10 to one, thereby determining the mode of reading the programmable digital signal generator. Positive impulses from address addressing and the other input of the second subtractive counter50 OD enter the counting input

9. In the recording mode through the highway-second subtractive counter 9,

A new communication line 5 is issued digitally, which starts to work on subtracting a parallel code, corresponding, setting each pulse to

the duration of the pulse series of the output-input and the address supplied on the information information to the input b occurs the 55th entry of the element I 7, which

writing to the second subtraction counter is then passed through the OR element

9, to the first input 2 of the IPI 66 element to the address input n of the memory block 8,

the address is displayed, and the information address is reached. When the value reaches zero

input input of block 8 of memory — output — second subtractive counter 9 of output 15221876

On the information, at the same time, O comes to the second input U of the element OR 6, since the control input of the element And 7 is set at this time

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O, due to the value of the input 6. , and writing to the memory block 8 of the output information at the addresses takes place through the element OR 6 at the address input n of the memory block 8. The code recorded in register 4 of the pulse duration code, corresponding to the clock duration of the output information, arrives at the 5th input b of the preliminary recording of the first subtractive counter 2, which does not change until the next recording cycle, controls the recording of the specified code into the first subtractive input counter 2 and prohibits the passage of the reference frequency from the output q of the master oscillator 1 to the counting input jk. first subtraction counter 2.

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Upon receipt of the input to the node 3 of the control by starting the counter, the reference frequency is passed to the counting input to the first subtractive counter 2, and the counter 2 begins to subtract from the code recorded at the pre-recorded input b. When the first subtractive counter 2 is installed, the zero position at the output and the first subtractive counter 2 to generate a positive pulse, which, entering the control unit 3 for starting the counter, is delayed by one clock of the master oscillator 1 and fed to the input to set the first subtractive counter 2 to its original state, i.e. recording the pulse duration code 5, the first positive pulse sets the output / output of the address control node 10 to one, thereby determining the mode of reading the programmable digital signal generator. Positive impulses with you;

at the output, a loan which sets the adress control node 10 to the zero state. It also prohibits the issuance of an address from the second subtractive counter 9 at the output of the And 7 element, and the read cycle is over. The timing diagram p reflects the operation mode of the memory block 8 and the programmable digital signal generator.

Claims (1)

Invention Formula The digital signal generator containing the master oscillator j is the pulse length code register, the start control counter node, the OR element, the AND element, and the information input of the pulse duration code register is connected to the generator pulse start reference input connected to the generator start input, which is due to the fact that, in order to expand the class of problems to be solved by increasing the duration of a series of pulses at a given frequency, they entered two of you itayuschih counter address issuance control unit and a memory unit, wherein the data memory unit is connected to the data input of input gene-, Rathore, address assignments whose input is connected to the first input element one ten 15 20 25 thirty 35 SH, the second input of which is connected to the output of the element AND, the output of the element OR is connected to the address input of the memory unit, the output of which is connected to the generator output, the output of the register of the duration code, pulse is connected to the preliminary recording input of the first subtractive counter, the counter and the control input connected respectively to the outputs. reference frequency and resolution rewrite control unit launch the counter whose input input pulses are connected to the output of the generator generator, the overflow output of the first subtractive counter is connected to the transfer control input of the counter start control node, the address control output mode setting input and the second subtracting counter count input, the input the preliminary recording of which is connected to the input of the task for the duration of a series of output pulses of the generator, the start input of which is connected to the control inputs of the second subtractive counter ... and the control node output The address of the address whose output is connected to the first input of the And element, the second input of which is connected to the information output of the second subtractive counter, the overflow output of which is connected to the stop input of the control node of the address. ig.2 FIG.