SU1677852A2 - Pulser - Google Patents

Abstract

The invention can be used in automation and computing devices for producing controlled pulse sequences. The purpose of the invention is to increase reliability by eliminating faulty situations in stop modes and restarting the generator. In the generator, when the power is turned on, the installation unit 26 produces signals that prepare the generator for operation. From busbars 13 and 23, registers 12 and 22 register information about the parameters of the generated sequence. The signal on bus 6 counters 9 and 21, into which information is rewritten from registers 12 and 22, starts counting the pulses of the reference frequency. The pulses that pull the counter 9 or 21 arrive, respectively, at the output of the AND 8 or AND elements 20, the trigger status changes. 25, thereby forming a predetermined sequence of pulses on the bus 11. To stop the generator, the bus 16 is given a signal, which stops the pulse of the reference frequency from bus 5 to the inputs of counters 9 and 21. To restart the generator, bus 6 is again fed to the control signal . The pulse generator also contains triggers 1, 2, 15, 17, 19, 25, elements AND 3, 4,14, 18, 24, the element OR 7 and the delay line 10. 2 Il. f About VJ VI 00 ate N) u

Description

The invention can be used in automation and computing devices and concerns the improvement of the generator according to auth. No. 1406735.

The aim of the invention is to increase the reliability of the generator,

FIG. 1 shows a structural diagram of a pulse generator; in fig. 2 shows an example of the execution of an installation unit.

The pulse generator (figure 1) contains the first trigger 1, the second trigger 2, the first element And 3, the second element And 4, the bus 5 pulses of the reference frequency, the start bus 6, the element OR 7, the third element And 8, the first counter 9 pulses, delay line 10, output bus 11, first register 12, period code bus 13, fourth element I 14, third trigger 15, bus 16 stop, fourth trigger 17, fifth element And 18, fifth trigger 19, sixth element And 20, the second counter 21 pulses, the second register 22, the bus 23 code duration, the seventh element And 24, the sixth trigger 25, block 26 installation,

Bus 6 is connected to, the installation input of the first trigger 1, the counting input of which is connected to the first input of the element OR 7, to the output of the first element AND 3 and the counting input of the second trigger 2, the output of which is connected to the first input of the second element And 4, the second input of which is connected bus 5 and the first inputs of the first and fifth elements And 3 and 18, and the output is connected to the subtractive input of the first counter 9, the first inputs of the third and seventh elements And 8 and 24. The second input of the third element And 8 is connected to the direct output of the first bit yes first counter 9, inv The digital outputs of the remaining bits of which are connected to the remaining inputs of the third element AND 8, the output of which is connected to the second input of the OR element 7, the output of which through the delay line 10 is connected to the read inputs of the first and second registers 12.22 and directly to the first input of the sixth trigger 25, the second input of which is connected to the output of the sixth element I 20, and the output connected to the output bus 11 and the second input of the seventh element And 24, the output of which is connected to the first input of the sixth element And 20 and the subtractive input of the second counter 21, the direct output of the first bit and the inverse outputs of the remaining bits of which are connected to the inputs of the sixth element I 20. The bus 16 is connected to the installation input of the third trigger 15, the output of which is connected to the first input of the fourth element And 14, the second input of which is connected to the bus 5, and the output - with the counting input of p

trigger 19, the output of which is connected to the third input of the second element 14. The input of the installation unit 26 is connected to bus 6, the first output is connected to the zeroing input of the first trigger 1, the second output is connected to the zero input inputs of the first and second counters 9, 21, triggers 2, 15,17 and 25 and the installation of the installation of the first trigger 19, the output of which is connected to the third input of the fourth

0 element And 14, the fourth input of which is connected to the inverse output of the sixth trigger 25.

The installation unit 26 (FIG. 2) contains a voltage divider across resistors 27, 28,

5 between the midpoint of which and the ground is on the capacitor 29. In addition, the midpoint of the divider is connected to the input of the Schmidt trigger 30, the inverse output of which is connected to the first input of the element

0 OR 31 and the first output 32 of the unit 26 installation. The second input of the OR element 31 is connected to the bus 6, and its output is the second output 33 of the installation unit 26,

The pulse generator works as follows.

When the power is turned on, the inverse output of Schmidt’s trigger 30 is set to 1. At the outputs 32.33 of the setup unit 26, there are high potentials. Triggers 1,2, 17, 25,

0, the counters 9 and 21 are set to O, and the trigger 19 is set to 1. Then, the bus code 13 receives the code of the number N, which is written to the first register 12. The number N characterizes the specified pulse following period

5 on the output bus 11; Bus 23 receives the code of the number M, which is recorded in the second register 22. The number M characterizes the specified pulse duration on the output bus 11, with M N.

0 With the arrival of the control signal to the bus 6 on the output 33 of the unit 26, the unit state of the flip-flop 19 and the zero states of the flip-flops 2.17, 25 and counters 9 and 21 are confirmed. The flip-flop 1 goes to

5 state 1, opening the fifth element And 18. The first pulse from the bus 5 pulses of the reference frequency after the control signal passes through the fifth element And 18 and the back front translates the fourth

0 trigger 17 to 1, opening the first element AND 3. A chain of the fifth element AND 18 and the fourth trigger 17 serves to prevent the cut-off pulse of the reference frequency from passing to the output of the first element AND 3 with an unfavorable timing ratio of the control signal on bus 6 and pulse frequency reference, which can lead to failure of the generator. The next pulse of the reference frequency passes to the output of the first element And 3,

passes through the element OR 7 to the first input of the sixth trigger 25, sets it to 1 and thereby forms the leading edge of the output pulse through the bus-11. In addition, the pulse from the output of the element OR 7 passes to the input of the delay line 10, where it is delayed by a time equal to G3. From the output of the delay line 10, the pulse arrives at the readout inputs of registers 12 and 22. From the first register 12 to the first counter 9, the chils code is entered N, and from the second register 22 to the second counter 21 - the code of the number M. The first pulse passing through the first element I 3 also goes to the counting inputs of the first and second triggers 1 and 2 and transfers the first trigger 1 to the state O on the falling edge. , prohibiting the passage of subsequent and the reference frequency pulses to the counting input of the fourth trigger 17, and the second trigger 2 to state 1. The same pulse of the reference frequency through the fifth element I 18 passes to the counting input of the fourth trigger 17 and by the falling front transforms it to 0y. pulses of the reference frequency at the output of the first element And 3. The second trigger 2 opens the second element And 4, which passes all subsequent pulses of the reference frequency to the subtracting input of the first counter 9, the first input of the third element And 8 and the first input of the seventh ementa and 24, the second input of which is open high potential output from the sixth flip-flop 25.

Pulses of the reference frequency received at the subtractive inputs of counters 9 and 21 are subtracted from their contents one by one. When the contents of the second counter 21 becomes equal to one, t, e. M-1 pulses of the reference frequency will be sent to its subtracting input, high potentials are set at the outputs of all bits of the second counter 21, the sixth element I 20 will open. The M-th pulse passes through the sixth element I 20 and enters the second input of the sixth trigger 25, transferring it to the state O, forming the rear edge of the output pulse. The low potential from the output of the sixth trigger 25 closes the seventh element I 24, prohibiting the passage of the reference frequency to the subtracting input of the second counter 21. At the same time, the Mth pulse on the trailing edge subtracts 21 units from the content of the second counter to zero.

The pulses of the reference frequency continue to flow only to the subtracting input of the first counter 9. When its content becomes equal to one, i.e. N-1 pulses of the reference frequency will go to its subtracting input, high potentials will be set up at the outputs of all bits of the first counter 9, the third element 8 will open. N-th pulse passes through the third element And 8, the element OR 7 and enters the first

input of the sixth trigger 25, transfer it to 1, forming the leading edge of the next output pulse. In addition, the Nth pulse is fed to the input of the 10 delay line.

At the same time, the Nth pulse on the falling edge subtracts 9 units from the contents of the counter, making it equal to zero. From the output of the delay line, the pulse arrives at the readout inputs of registers 12 and 22. If the information in the registers has not changed, the whole process will be repeated cyclically. On the output bus 11, a pulse sequence will be formed, determined by the numbers N and M. If other numbers are written to the registers, then the parameter of the next output pulse will be determined by the new values of N and M.

To avoid the simultaneous arrival of N-ro and M-th pulses at the subtracting inputs of counters 9 and 21 and the arrival of information from registers-12 and 22 to the installation inputs of counters 9 and 21, the delay time of delay line 10 is selected.

te r3 te,

where T3 is the delay time of the delay line;

h, Te is the duration and period, respectively, of the following pulses of the reference frequency.

If it is necessary to stop the pulses on the output bus 11, a control signal is received from the stop bus 16 to the input of the third trigger 15, which translates the trigger 15 to 1, opening the fourth element I 14 at the first input. If there is a high potential on the output bus 11 the formation of the output pulse of the generator), the element And 14

turns out to be closed at the third input by a low potential from the inverse output of the sixth trigger 25. Thus, the possibility of the appearance of a cut-off pulse on the output bus 11 when the

receipt of the control signal from the bus 16 stop. At the end of the pulse on the output bus 11 (or directly from the control signal from the bus 16 stop if there was no output pulse on the bus 11) the fourth element I 14 turns out to be an open high potential from the inverse output of the sixth trigger 25. The first pulse of the reference frequency passed through the fourth element I 14, at the counting input with the falling edge translates the fifth trigger 19 into O, closing the second element I 4 and stopping the issuance of the reference frequency pulses to the subtracting inputs of counters 9 and 21. At the same time, the potential is low From the output of the trigger 19, the fourth element AND 14 is closed at the third input, thereby excluding the possibility of changing the state of the fifth trigger 19 in the stop mode.

If the generator is restarted, a control signal is sent to the start bus 6, by which the first trigger 1 is set to 1, the block 26 at output 33 generates a signal that sets the triggers 2, 15, 17, 25 and the counters 9 and 21 to the state Oh, and trigger 19 is in state 1, after which the generator resumes its operation.

Thus, the introduction of the installation unit 26 and the organization of new connections make it possible to organize reliable operation of the generator as in the stop mode by eliminating the possibility of generating pulses at the generator output in this

mode, and in the restart mode, by bringing the generator back to its initial state each time it is restarted. The formula of the “invention” Pulse generator according to the author

No. 1406735, characterized in that, in order to increase reliability, an installation unit is inputted into it, the input of which is connected to the start bus, the first output from the first trigger input, the second output to the zero and first pulse counters, second, third, the fourth and sixth flip-flops and the setup input of the n-th flip-flop

connected to the third input of the fourth element And, the fourth input of which is connected to the inverse output of the sixth trigger.

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Claims (1)

Claim Automatic pulse generator No. 1406735, characterized in that, in order to increase reliability, an installation block is introduced into it, the input of which is connected to the start bus, the first output is with the zeroing input of the first trigger, the second output is with the zeroing inputs of the first and second pulse counters, of the second , the third, fourth and sixth triggers and the installation input of the fifth trigger, the output of which is connected to the third input of the fourth element And, the fourth input of which is connected to the inverse output of the sixth trigger. FIG. g