SU659976A1 - Digital frequency meter - Google Patents

Description

The scheme contains a controlled frequency divider 1, a block 2 of formation and control, a / p-decade counter 3, a generator of 4 clock pulses, an additional element AND 5, a delay element with taps, a block 7 of controlled keys, a frequency divider 8, an input of meter 9 , result counter 10, (t + «) - decade counter AND, elements AND 12, elements OR 13, decades 14, control triggers 15 and logical elements AND 16.

The meter works as follows.

When a signal of unknown frequency (for example, a sinusoidal oscillation or a sequence of pulses with an unknown frequency) arrives at the device input, the formation and control unit 2 generates a start-stop pulse whose duration is equal to the input signal period or more than the input signal period of 10, 100, 1000 and t D times (depending on the value of the division factor of divider 1). The division factor can be adjusted within 1: 1, 1: 10, 1: 100, etc. The start-ston impulse from the output of block 2 simultaneously enters the first inputs of all elements And 12, by opening (connecting) interdecade communications of counter 3. As a result, the counter 3 for the duration of the start-stop pulse is filled with the pulses of the clock generator 4 having a period TO.

At the end of the start-stop pulse, elements And 12 at the first input are closed, the connection is disconnected between the decades. At the same time, unit 2 generates a pulse, which from its second output goes to the second input of element 5, the first generator of which is connected to a clock generator 4. From the output of element 5, pulses follow to delay element 6 and through it from the corresponding taps to the input of element OR 13, to the inputs of block 7 (inputs of the AND 16 circuit of the logic element) and the input of the divider 8 with a division factor of ten. The moment of arrival of a pulse from the output of block 2 to the input of element 5 is the beginning of the census in the counter of the 11th number recorded in counter 3. The period of one census cycle is equal to ten periods of the clock frequency. In time equal to ten TO of counter 3 to counter 11, the value of the time interval Tx is rewritten in a digital code. In this case, in counter 3, the information after the census Tx is stored. The census is made from all t decades 14 of counter 3 in the first t decades of counter 11 simultaneously, since the output of the first decade of counter 3 is connected via the corresponding key of block 7 to the input of the first decade of counter I, the output of the 2nd decade through corresponding key and OR element 13 - with the input of the 2nd decade, the output of the 3rd decade - with the entrance of the third decade of the counter 11, etc. Each of the keys of the block 7 opens for exactly the time that allows the passage of so many pulses of the clock generator 4, how many of them were recorded in the corresponding decade counter 3. For example, in the first decade of counter 3, the number “4 (four) was recorded. Census (record) of the same number in the first decade of the counter

11 happens as follows. According to the command from block 2 of formation and control, the clock generator pulses go through the corresponding (in this case, the first) delay element to the OR 13 element and to the input of the first decade of the counter 3. Since the decade contains the number four, after passing five pulses the decade ( the elementary counter will fill in the next pulse

will be an overflow pulse, which is at the output of the decade and will open the first key of block 7. Due to the fact that the second input of this key receives pulses from the clock generator 4 (the first

retraction of the delay element 6) and they have a normalized duration, then only the 7th pulse passes through the key and enters the input of the first decade of the counter I, divisor 8 and counter 10. Then all the keys

unit 7 is closed with a pulse received from the output of divider 8 with a division factor of ten, which also receives clock generator 4 from the output of delay element 6. Thus, all the keys of unit 7 are closed at the same time and opened each time. It depends on what number is stored in the corresponding decade of counter 3. The census value process

the digital code from counter 3 to counter 11 will occur until counter 11 overflows. An overflow impulse is supplied to the formation and control unit 2, which generates a signal

prohibiting the passage of pulses of the clock generator 4 through the element AND 5. The number of cycles in the census of the counter 3 code is recorded in the counter 10 of the measurement result in hertz. This measurement process ends.

Claims (2)

1. USSR author's certificate number 391728, cl. H OZK 13/20, 1972. 2. US patent number 3842347, cl. 324-7 SD, 1974. gys