SU1478323A1 - Controlled pulse-rate frequency divider - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital measuring equipment, in frequency synthesizers, in automation and telemechanics devices. The aim of the invention is to increase the reliability of the device while simplifying it. This goal is achieved by ensuring the guaranteed pulse duration of setting the pulse counter to the required state with even and odd division factors. The device contains a pulse counter 4, triggers 1,3,11 and 13, a code comparison element 5, a control block 6, elements AND 7.8 and 9, an OR element 10, input and output buses 2 and 12. 1 Il.

Description

The invention relates to a pulse technique and is intended for use in digital measuring equipment, in frequency synthesizers, in automation and telemechanics devices.

The aim of the invention is to increase the reliability of the device while simplifying it.

The drawing shows an electrical structural scheme of a controlled pulse frequency divider.

The controlled pulse frequency divider contains the first trigger 1, the counting input of which is connected to the input bus 2, the output to the first setup input of the second trigger 3 and the counting input of the n-bit counter 4 pulses, the outputs of the bits of which are connected to the first group inputs of n-bit code comparison element 5, the second group of inputs of which is connected to the outputs of the higher bits of the (n + 1) -disk control unit 6, the output to the second installation input of the second trigger 3, the output of which is connected to the first (right ) entrance The first element And 7 and the first input of the second element And 8, the second input of which is connected to the output of the third element And 9, the first input of which is connected to the output of the low-order (n + 1) -disk control unit 6, and the second (inverse) the input of the first element And 7, the output of which is connected to the first input of the element OR 10 and to the input of the installation in O n-bit counter 4 pulses, the input of the installation in 1 of which is connected to the output of the second element And 8 and to the counting input of the third trigger 11, the installation the input of which is connected to the output of the lower bit and n-bit counter 4 pulses output - to a second input of the OR gate 10, whose output is connected to the output Shino 12 minutes and counting input of the fourth flip-flop 13, whose inverse output coupled to a second input of the third AND element 9.

To store the code of a given coefficient K, a (n + +1) -based control unit 6 is designed for d division, the most significant bits of which are connected to the second group of inputs of the n-bit code comparison element 5, which provides a comparison of the code equal to 0.5 K

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with even K or equal to 0.5 (K-1) with odd K.

The device works as follows.

Counting triggers of the device are triggered by the falling edge of the pulses arriving at their inputs.

The installation of the counter 4 in the state O or 1 is made by the signals of the unit level. The trigger 11 is set (to zero) with a zero level signal, and the trigger 3 is set with unit level signals.

In the initial state, the triggers of the counter 4, as well as the triggers 1,3,11 and 13, are set to zero states. The code of the specified division factor is recorded in block 6. When dividing into even coefficients in the lower-order control code, zero is written. The zero-level signal from the low-bit output of block 6 enters the input of element 9. Regardless of the 25 conditions of trigger 13, the signal at the output of element 9 is zero, with the result that when divided by even coefficients, element 7 is open and element 8 is closed .

When counting input pulses coming through bus 2, the state of flip-flop 1 and flip-flops of counter 4 change. When counting the K-th input pulse, the code of 0.5 K is set at the outputs of counter 4. At the output of element 5, the unit level by which the trigger 3 is set to the unit state. The unit level signal from the output of the trigger 3 is fed through the open element 7 to the input of the installation in O of the counter 4 and to the input of the element 10. The triggers of the counter 4 are set to zero states, and a single level signal appears on the bus 12.

At the moment of termination of the (K + 1) th input pulse, trigger 1 goes to one state and by its output signal trigger 3 is set to zero. This stops the reset of the counter 4 and ends with the formation of the output pulse on the bus 12.

5 This ends the first cycle of dividing the input pulses by the specified ratio if the number K is even. Further in the division

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five

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at even factors, the operation of the device is repeated.

When divided by odd factors in the low-order bit, the control code is recorded 1. The unit-level signal from the lower-bit output of block 6 is fed to the input of element 9. The signal at the output of element 9 is determined by the state of trigger 13. In the initial state, trigger 13 set to zero. Therefore, in the first cycle of dividing the input pulses by an odd coefficient, the signal at the output of element 9 is equal to 1, with the result that element 7 is closed and element 8 is open.

When counting the (K-1) th input pulse from bus 2, the code of the number 0.5 (K-1) is set at the outputs of the bits of counter 4. In this case, a single level signal appears at the output of element 5, with which the trigger 3 is transferred to the single state. The signal of the unit level from the output of the trigger 3 is supplied through the open element 8 to the input of the installation in 1 of the counter 4 and to the counting input of the trigger 11. The triggers of the counter 4 are set to single states.

At the moment the K-th input pulse terminates, the trigger 1 is set to one state and, by its output signal, the trigger 3 is set to the zero state. In this case, the signal at the output of element 8 becomes zero, as a result of which the trigger 11 goes into one state and a single level signal appears on bus 12.

At the moment of termination of the (K + 1) th input pulse on bus 2, the trigger 1 is set to the zero state, as a result of which the triggers of the counter 4 are also set to zero-co. The zero-level signal from the low-bit output of the counter 4 sets the trigger 11 to the zero state, as a result of which the formation of the output pulse on the bus 12 ends, and the trigger 13 is switched to the single state. The signal at the output of element 9 becomes zero, element 8 closes, and element 7 opens.

In the second division cycle, the odd factor in the calculation of (k + 3) th input pulse in unit 4 sets the unit code;

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five

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Those (K + 5) -th input impulse - the code of the number two, etc. When counting the 2 K-th input pulse at the outputs of the counter 4, the code number 0.5 (K-1) is set. In this case, a single level signal appears at the output of element 5, trigger 3 goes into one state, counter 4 triggers are set to zero, and an output pulse appears on output bus 12.

At the time of termination of the (2K + 1) th input pulse, trigger 1 is set to one, trigger 7 is transferred to the zero state, installation of the triggers of counter 4 stops at zero, and the output pulse on bus 12 is completed. At that, trigger 13 is set to the zero state, element 7 is closed, and element 8 is opened.

Subsequently, the operation of the device is repeated by double cycles, at the end of odd cycles, the counter 4 is set to one state, and at the end of even cycles to the zero state.

Claims (1)

Invention Formula A controlled pulse frequency divider containing the first trigger, the counting input of which is connected to the input bus, and the output connected to the first setup input of the second trigger and the counting input n-bit of the pulse counter, the outputs of the bits of which are connected to the first group of inputs n -discharge comparison code element, the second group of inputs of which is connected to the outputs of the higher n bits (n + 1) -discharge control unit, the output with the second installation input of the second trigger, the output of which is connected to the first input ne And the first input of the second element And, the second input of which is connected to the second input of the first element AND, the output of which is connected to the first input of the OR element, the output of which is connected to the output bus, the second input to the output of the third trigger, the counting input of which is connected to the output of the second element I, the setup input — with the output of the low-order n-bit pulse counter, and the fourth trigger, о t - 51D783236 characterized by the fact that, from the target, with the inverse output of the fourth one, which improves reliability at the same time, the counting input of which is variable simplified, is introduced into it with the output bus, and the input element The units in O and in 1 n-bit are connected to the second input of the first elemental pulse counter connected to the AND, the first input to the output below the outputs of the first and th bit of the control unit, the second second element I.