SU1596453A1 - Pulse recurrence rate divider - Google Patents

Abstract

The invention can be used in digital instrumentation, in frequency synthesizers, and in automation devices. The purpose of the invention is to increase the working frequency range when dividing by odd division factors - achieved by introducing the element I 13, executing the control unit 6 in the form of a combinable adder and organizing new functional connections. The device also contains a pulse counter 1, a rotary decoder 4, a control code decoder 5, triggers 7-9, an AND-NE element 10, a reset pulse shaper 14, elements 11 and 12, input and output buses 15 and 16, and control code bus 17 . Symmetric output pulses are generated at the device output. 1 il.

Description

The invention relates to a pulse technique and can be used in 1-DIFFER measuring equipment, frequency synthesizers in automation devices.

The purpose of the invention is to increase the operating frequency range when dividing into odd division coefficients.

The drawing shows an electrical structural scheme, devices,

The pulse frequency divider contains a pulse counter 1 consisting of a serially connected counting trigger 2 and a pulse counter 3, a duty cycle decoder 4, a control code decoder 5, a control block 6 executed in the form of a combinational adder first, second and third triggers 7.8 and 9, the AND-NE element 10, the first, second and third elements AND 11, 12 and 13, the driver 14 of the reset pulses, the input and output buses 15 and 16, and the bus 17 of the control code. The outputs of the bits of the counter 1 pulses, except the older one, and the outputs of the bits of the counter 1 pulses, except the younger one, are connected to the first groups of inputs, respectively, of the decoding 4 of the duty cycle and the decoder 5 of the control code, the second groups of inputs of which are connected to the outputs of the bits, except the younger, block 6 controls, the inputs of which are connected to the bus 17 of the control code; The output of the decoder 4 of the duty cycle is connected to the first input of the first element 11, the output of which is connected to the start input of the second trigger 8, the second input to the output of the I- element E 10, the first input of which is connected to the input bus 15 and the counting input of the pulse counter 1 (with the counting input of the counting trigger 2), the reset input of which (the reset input of the pulse counter 3) is connected via the reset pulse driver 14 to the output of the control code decoder 5 and directly with the first (direct) input of the second element I 12 and with the second input of the third trigger 9, the information input of which is connected to the second (inverse) input of the second element 12, with the output of the lower bit of the control unit 6 and with the information input the first trigger 7, the output (direct) of which is connected to the reset input of the third trigger 9 and to the first input of the lower bit of the control unit 6, the second input of the lower bit of which is connected to the second input of the AND-NE element 10. The first input of the third element I 13 connected to the low-voltage output of pulse counter 1, the second input to the output (direct) of the third trigger 9, the output to the reset input of the second trigger 8, the direct output of which is connected to the output bus 16, the inverse output to the clock input of the first trigger 7. Counting input of the second trigger 8 is connected to the output of the second element And 1

The maximum value of the division factor K. is determined by the capacity of the counter 1.

At the outputs of the decoders 4 and 5, the signals of the unit level are formed at the moments of coincidence of the codes arriving at the first and second groups of inputs of these decoders.

At the outputs of block 6 there is either a code of a given division factor K, received 1st bus 17, under the condition that trigger 7 is in the zero state, or code of the number K + 1 if trigger 7 is switched to one state.

The second group of inputs of decoders 4 and 5 from the outputs of block 6 receives a code of the number K or K + 1, shifting one bit in the direction of the lower bits,. code of the half-factor drleii.

Triggers 7 and 9, as well as elements 10 and 13, provide control over the operation of the device when dividing into odd factors. .

I

The device works as follows

Before the device starts operation, the triggers of the counter 1, as well as the triggers 7, 8 and 9, are set to zero conditions (the installation circuits are not shown), and the code of the specified division factor K is supplied to the buses 17 of the control code.

Claims (1)

If the number K is even, then in the mdpd code of this number contains zero. The zero signal from the bus of the lower bit of control code 17 goes to the second input of element 10, resulting in the output of this element when divided by. Even coefficients the signal of the unit level is constantly present, with which element 11 is constantly open, and the signals from the output of the decoder 4 can freely pass through element 11 to the trigger trigger input 8. At the output of the lower bit of block 6 when dividing by even coefficients, a zero signal is lost. This signal goes to the information inputs of the trigger 7 and 9 and to the second input of the element 12, as a result of which the triggers 7 and 9 when divided by the even coefficients remain zero states, the element 12 is constantly open, allowing the signals from the generator 14 to pass the counting input of the trigger 8, the element 13 is permanently closed and the device works with the manual in the same way. When calculating the 0.5K-th input pulse from the bus 15, the code of the number 0.5K is generated at the outputs of counter 1. In this case, the decoder 4 is triggered and its output signal through the open element 11 is triggered by the switch 8 to the state of one. On the bus 16, an output pulse appears. When calculating the K-th input pulse, the code of the K number is generated at the outputs of counter 1, and the code of the number 0.5 K at the outputs of counter 3. In this case, the decoder 5 triggers and its VIC signal triggers the shaper 14. The signal from the shaper 14 is fed to the reset input of counter 1, and through the open element 12 - to the counting input of trigger 8. The counter 3 pulses is reset to its initial state, and trigger 8 goes to the zero state. In this case, the output pulse on the bus is not 16. In the future, when dividing by even factors, the operation of the device is repeated. When divided by odd factors, the low-order control code contains a .unit. The unit-level signal from the low-order bus of the control code 17 is fed to the second input of element 10, the single signal at the output of element 10 appears in this case only pauses between the input pulses. Since the initial state of trigger 7 is zero, the code of the Co number is set at the outputs of block 6. At the same time, the code of the number 0.5 (K-1) is fed to the second groups of inputs of decoder 4 and 5, and the information inputs of the trigger 7 and 1 3 9 and to the second input of element 12 from the output of the low-order bit of BLACK 6 — a signal of a single level. Triggers 7 and 9 are prepared for transition to single states, and the counting input of the trigger 8 is disconnected from the output of the driver 14 and the device operates as follows In the case of counting 0.5 (K-1) th input The first pulse is triggered by the decoder 4 and its output signal is fed to the second input of element 11. At the moment of the 0, 5 (k-1) -th input pulse, element 11 is open and the signal from the output of the decoder 4 is fed to the input of the trigger trigger 8 o Trigger 8 goes An output pulse appears in the unit state and on bus 16. When counting the (K-1) th input pulse, the decoder 3 is triggered and the shaper 14 is started. The signal from the shaper 14 output to the reset input of the counter 1 resets the counter 3 to the initial state. The same signal arrives at the clock trigger input for 9, which leads to its transition to the unit state. The unit level signal from the trigger output 9 goes to the second input of the element 13. At the first input of the element 13 at this time there is a zero level signal, since after each even input pulse is counted, trigger 2 is in the zero state. When counting the next K-th input pulse, the tri-. The ger 9 goes to the single state, as a result of which the output of the element 13 appears a single level signal, which enters the reset input of the trigger 8, sets it to the zero state. At the same time, the output pulse on the bus 16 ends, and at the clock input of the trigger 7, a single level signal appears, which triggers the trigger 7 to a single state. The signal of a single level from the output, trigger 7 is fed to the reset input of trigger 9 and to the first input of the low-order bit of block 6. In this case, the trigger 9 returns to its initial state, and the code of the K + 1o number is set at the outputs of block 6. This completes the first cycle device operation when dividing by odd factors. The state of the device before the second operation of dividing by odd coefficients differs from the initial one in that counter 1 contains one (since K is an odd number), and the second groups of inputs of the decoders L and 5 receive the code number 0, 5 (K + 1). Therefore, in the second cycle of dividing by odd coefficients, the device operates as follows. When counting (K + 0.5 (K-1)) -th input pulse at the outputs of counter 1, the code of the number 0.5 (K-1) +1 0 is formed, 5 (K + 1), as a result of which the decoder 4 is triggered and its output signal, after the end (K + 0.5 (K-1)) of the input pulse, the trigger 8 is switched to one state. When calculating the 2K input pulse, the code of the number K + 1 is generated at the outputs of counter 1, and the code of the number 0.5 (K + 1) is generated at the outputs of counter 3. In this case, the decoder 5 is triggered, the driver 14 is started and the counter 3 is reset, the trigger 8 goes to the zero state. When the trigger 8 goes to the zero state, the trigger 7 also switches to the zero state, as a result of which the outputs of block 6 are set to numbers K and. the device is restored to its original state. Subsequently, when dividing by odd factors, the operation of the device is repeated in double cycles. The invention The pulse frequency divider containing a pulse counter, the outputs of which bits, except the youngest, and the outputs of the bits of which, except the older, are connected to the first groups of inputs, respectively, of the control code decoder and the duty cycle decoder, the second groups of inputs are connected to the outputs in addition to the low-order control unit, the inputs of which are connected to the control code buses, the low-level output is connected to. the information input of the first trigger, the second trigger, the direct output of which is connected to the output bus, the start input — with the output of the first element I, the first input of which is connected to the output of the duty cycle depressor, the second input — with the output of the NAND element, whose first input is connected to an input bus and with a counting input of a pulse counter, the reset input of which is connected to the first input of the second element I and through the reset pulse shaper to the output of the decoder of the control code ININ, and a third trigger, characterized in that the frequency range when dividing into odd - division factors, the control unit is made in the form of a combinational adder and the third element I is entered, the first input of which is connected to the low-voltage output of the pulse counter, the output - to the reset input of the second trigger, the second input - the output of the third trigger, the clock input of which is connected to the reset input of the pulse counter, and the information input to the output of the lower bit of the control unit and to the second input of the second element I, the output of which is connected to the counting input the second trigger, the inverse output of which is connected to the clock input of the first trigger, the output of which is connected to the reset input of the third trigger and to the first input of the lower section of the control unit, the second input of the lower level of which is connected to the second input of the AND NAND element,