SU1670789A1 - Divider of pulse repetition frequency with fractional count-down ratio - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation devices, computing and measuring equipment. The purpose of the invention is the expansion of functionality by providing a fractional division factor is achieved by the formation of new functional connections. The divider contains counters 1, 8 pulses, elements of comparison 3, 6 codes, bus 4, 7, 2 and 5 first code, second code, reference frequency and output, respectively. 1 il.

Description

The invention relates to a pulse technique and can be used in automation devices, computing and measuring equipment.

The purpose of the invention is the expansion of functionality by providing fractional division coefficient.

The drawing shows the electrical • structural diagram of the proposed device.

The pulse frequency divider with a fractional division coefficient contains the first pulse counter 1, the counting input of which is connected to the reference frequency bus 2, the information outputs are connected to the first group of information inputs of the first code comparison element 3, the second group of information inputs of which are connected to the first code bus 4. the output is to the output bus 5. and the control input is to the output of the second code comparison element 6, the first group of information inputs of which are connected to the second code bus 7, and the second group of info input inputs - to the information outputs of the second counter 8 pulses, and the output of the first element 3 code comparison is connected to the installation input of the first counter 1 pulses and the counting input of the second counter 8 pulses.

The device operates as follows.

In the initial state, the outputs of both counters have a zero code. The first group of tires 4 sets the code of the integer part of the division coefficient of the device. The output of the first element 3 comparison logical zero. The logical unit appears at the output of the comparison element 3 only when the counter code 1 is equal to or greater than the code set on the tires 4. On the buses 7, the code for the fractional part of the division coefficient is specified. At the output of the second comparison element 6 there is a signal of a logical unit. A logical zero appears at the output of the comparison element 6 when the counter code 8 becomes no less than the code on the buses 7.

When pulses of frequency f _{0 are} received from the input bus 2 to the counter input of counter 1, the code at its outputs starts to increase and at some point becomes equal to the code on the buses 4. However, since there is a logical unit signal at the control input of the comparison element 3, the signal at the output of comparison element 3 will appear only when the code of counter 1 exceeds the code on tires 4. If, for example, the code number N is specified on buses 4, the signal of a logical unit will appear at the output of comparison element 3 when there is a code on the outputs of counter 1 (N + 1). The signal from the output of the comparison element 3 sets counter 1. to its initial state, which again starts counting pulses of frequency f ₀ , and enters the input of counter 8. Counter 8 has a conversion factor K, i.e. after receipt of K pulses at its input, it is set to its original state. If the code of the number n is set on the buses 7, then after the comparison element 3 generates η periods of the value Τ '= (Ν + 1) / f ₀ , the code of the number n is written in counter 8.

If the codes at the inputs of the comparison element 6 are equal, a logical zero will appear at its output, which will be present at the output of the element 6 until the counter 8 returns to its original state and the code at its outputs becomes less than the code on the buses 7. Since the input If the control element of the comparison element 3 receives a logic zero signal, the signal of the logical unit at the output of the element 3 appears when the counter code 1 becomes equal to the code on the buses 4, i.e. a period is formed with the value T '' = N / f ₀ . After the (Т - п) periods are formed by the value T, the counter 8 will be set to its initial state and the comparison element 3 will begin to form a sequence of pulses with a period Τ ', i.e. everything will be repeated again.

The average period for the cycle of operation of the counter 8 is equal to

Τ = (π Τ '+ (K - η) -T') / K = (N + J) / f ₀ .

Thus, the proposed device allows to obtain a fractional division coefficient. Under the condition η> K, the device allows you to divide the input frequency with an integer division factor.

The specific implementation of the comparison elements depends on which elements are used for their implementation and are determined on the basis of which series of chips the divider is running on, for example, the K561IP2 chip can be used as an element for comparing codes.

Claims (1)

Claim A pulse frequency divider with a fractional division coefficient, comprising a first pulse counter, the counting input of which is connected to the reference frequency bus, and the information outputs are connected to the first group of information inputs of the first code comparison element, the second group of information inputs of which is connected to the first code bus, output - to the output bus. and the control input - to the output of the second code comparison element, the first group of information inputs of which is connected to the second code bus, and the second 5 group of information inputs - to the information outputs of the second pulse counter, characterized in that, in order to expand the functionality by providing the possibility receiving both integer and fractional division coefficients, the output of the first code comparison element is connected to the installation input of the first pulse counter and the counting input of the second pulse counter.