SU1675885A1 - Multichannel device for connecting subscribers to common main line - Google Patents

Abstract

The invention relates to computing, can be used in systems that control access to a common resource. The purpose of the invention is to reduce equipment. The device contains a shift register 1, circuits 2, 8 comparison, trigger 3, two counters 4, 5, element 11, trunk amplifier 7, element 9, delay element 10. In the device, the comparison of priority codes occurs by successive bit-wise transmission over a common highway. 1 silt

Description

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The invention relates to computing technology, in particular to priority devices, and can be used in systems that control access to a common resource,

The purpose of the invention is to reduce the amount of equipment.

The drawing shows the structural scheme of the device.

The device contains a shift register 1, comparison 2, trigger 3, counters 4 and, element 6, trunk amplifier 7, comparison 8, element 9, delay element 10, delay element 10, acting as a delay element, common highway 12 , a device clock input 13, a device reset input 14, a device signal output 15 and a device request input 16.

The device works as follows.

After the power is turned on by the initial setup signal, which enters the input 14 of all channels at the same time, in all devices, the counter 4 is set to the zero state. In addition, due to the absence of signals at the first moment, the Request in all devices, counter 5 and trigger 3 are set to the zero state, and the shift mode is disabled for shift register 1. Thus, at the time of the absence of a signal, the Request and the presence of a signal at input 14 at the information inputs of the comparison circuit 8 are the same zero codes and the output of the comparison circuit 8 is high. The permissive signal from the output of the comparison circuit 8 is fed to the third input of element 6. At the second input of this element is received the resolving potential from the output of trigger 3. To the first input of element 6 is the clock frequency from output 13. The clock frequency from the output of element 6 is fed to the clock input of the shift register 1. In addition, from the input 13 of the device, the clock frequency enters through the e-element 10 of the delay to the clock input of the counter 4.

After the signal is removed from the input 14, the counter 4 changes its state with the arrival of each clock pulse of the maximum code value determining the priority of the device. The priority code is listed in a shift register operating in a cyclic shift mode. Counter 4 operates in a cyclical mode. Thus, at the output of the comparison circuit 8, an AND 6 signal for the element appears once per cycle of the counter. This continues as long as there is no signal at input 16. When a signal is received in several devices, the Request counter 5 of these devices is unlocked to

the time of occurrence at the output of the comparison circuit 8 of the enabling signal for the element And 6, which corresponds to the zero state of the counter 4. The element also unlocks

I / 111. At this moment, the clock pulse through the element And 6 enters the clock input of the shift register and through the element 11 to the clock inputs of the comparison circuit 2 and the counter 5.

0 On the leading edge of the clock pulse at the output of the shift register 1, the most significant bit of code appears, determining the priority of the device. The signal from the output of the shift register 1 through the unlocked main amplifier 7 is fed to a common highway. At the same time, the total potential of the INSTALLATION OR, which is fed to the first input, is established in the general highway 12

0 comparison circuit 2. The second input of the latter receives a signal from the output of the shift register 1. The comparison occurs on the high level of the clock pulse fed to the comparison circuit 2 through the element

5 11.

On the trailing edge of the clock pulse, counter 5 is activated and changes its state. The counter 4, like the counter 5, changes its state on the falling edge

0 clock pulse generated at the output of the element 10 delay. Thus, the counters 4 and 5 synchronously change their state, the output potential of the comparison circuit 8 is maintained

5 for the element of AND 6, and in the comparison circuit 2, a sequential comparison of priority codes is made, starting with the highest bit. If at the moment of comparison a low potential is present at the first input of the comparison circuit 2, and a high potential at the second input (output of the shift register), which indicates that there is a subscriber with a higher priority on the highway, then a positive differential is formed at the output of the comparison circuit 2. to which the trigger 3 is set to one state and blocks the element AND 6 with a negative potential from its inverse output. Thus, the proposed device

0 is excluded from arbitration.

If the device has the highest priority, after all the comparison cycles have been completed, a high level appears at the overflow output of counter 5, which through the inverter blocks the trunk amplifier 7 and arrives at the output of the device as an Accept capture signal. Further operation of the counter 5 is blocked. The initialization of the device is accomplished by removing the Request signal. Subscribers who have not received the Confirmation of Acquisition signal for two periods of arbitration after generating the Request signal remove the Request signal to reset the device to its original state and then can re-participate in the arbitration.

Claims (1)

Claims A multichannel device for connecting subscribers to a common highway containing in each channel a shift register, a first comparison circuit, a trigger, two counters, two AND elements, the first input of the first comparison circuit is connected to a common trunk, characterized by equipment, it contains a second comparison circuit, a trunk amplifier, a NOT element, and a delay element, and the shift register mode control input is connected to the first blocking input of the trunk amplifier, m input of the first element And, with the input of the initial installation of the first counter, with the reset input of the trigger and with the input of the device request, the clock input of the shift register is connected to the second input of the first element And and with the output The second element And, the first input of which is connected to the input of the delay element and the clock input of the device, the second input of the first comparison circuit is connected to the information input of the main amplifier and the output of the shift register, the output of the first comparison circuit is not connected to the trigger input of the first circuit the comparison is connected to the clock input of the first counter and with the output of the first element I, the information outputs of the first and second counters are connected to the corresponding inputs of the second circuit compared The equality output of which is connected to the second input of the second element I, the clock input of the second counter is connected to the output of the delay element, the second blocking input of the main amplifier is connected to the output of the element NO, whose input is connected to the overflow output of the first counter and the signal output of the device, the output of the main amplifier is connected with a common highway, the reset input of the device is connected to the reset input of the second counter, the inverse output of the trigger is connected to the third input of the second element I.