RU1837307C - Multichannel interface device for shared resource system - Google Patents

Abstract

The invention relates to computing and communications and can be used in distributed computing systems and local area networks to control access to a shared resource. The purpose of the invention is to expand the scope of the device by indicating the end of the arbitration. Each channel of a multi-channel device for connecting subscribers to a common resource contains three AND elements, two comparison circuits, two trunk amplifiers, two delay elements, a pulse shaper, two triggers, a shift register, and three counters. The device allows arbitration of requests to capture a shared resource when implementing persistent access methods with the exception of the influence of the arbitration time on the time a subscriber takes a shared resource and an indication of when the shared resource was captured. 3 ill. cl

Description

The invention relates to computing and communications and can be used in distributed computing systems and LANs to control access to a shared resource.

The purpose of the invention is to expand the functionality of the device by eliminating the influence of the arbitration time on the time of the subscriber’s capture of the total resource and organization of the capture indication | a shared resource when implementing persistent access methods. In FIG. 1 shows a block diagram of a device; figure 2 is an example implementation- | the first main amplifier; Fig. 3 - an example implementation of the second main | amplifier.

I- The device contains in each channel I a shift register 1, the mode control input of which, together with the blocking inputs of the first delay element 5 and the second main amplifier 7, as well as the initial setting of the second counter 10, are connected to the output of the first element And 12, the first input of which together with the input of the initial installation of the second trigger 14, connected to the input of the Request device 19, the second input of the first element And 12 together with the second input of the second element And 13 are connected to the output of the third counter 16, the first input to element And 13 is connected to the input device 19 Request, the output of the second element And is connected to the input of the initial installation of the first trigger, the inverse output of which is connected to the third input of the first element And, the clock input of the third counter 16 is connected to the clock input 21 of the device, the input is the initial

00 00

VI

Cj

about xj

the installation of the third counter is connected to the output of the pulse generator 15, the input of which together with the output of the first 4 and the input of the second 7 main amplifiers are combined along a common line 17, the output of the second main amplifier 7 is connected to the first input of the second comparison circuit 8, the second input of which together with the first input of the first main amplifier 4 is connected to the output of the shift register 1, the gate input of the second comparison circuit 8, together with the clock of the second counter 10, is connected to the output of the first delay element 5 and, the input of which, together with the clock input of the shift register 1, is connected to the output of the third element And 2, the first input of which is connected to the output of the first comparison circuit 9, and the second input, together with the input of the second delay element 3, is connected to the clock input of the device 21, the output the second delay element 3 is connected to the clock input of the first counter 6, the information inputs of the first comparison circuit 9 are connected to the corresponding outputs of the first 6 and second 10 counters, the overflow output of the second counter 10 is connected to the clock input of the second a trigger 14, the inverse output of which is connected to the second input of the first main amplifier 4 and to the output 20. Capture confirmation, the output of the second comparison circuit 8 is connected to the clock input of the first trigger t1, the input 18 of the initial installation of the device is connected to the input of the initial installation of the first counter 6, the input of the channel priority code is connected to the information input of the shift register (not shown in the diagram).

The device operates as follows.

After turning on the power by the signal of the initial installation N. Ust, received at the input of 18 devices of all channels

simultaneously, in all devices the counter

6 is set to the zero state. In addition, due to the absence at the first moment of signals. The request (bus 19) in all channels at the first inputs of the elements And 12 and 13 receives a low level signal. From the output of element And 12, this signal is input to the installation of the counter 10, keeping it in the zero state, it blocks the main amplifier 7, delay element 5, and the shift mode is prohibited for the shift register 1.

Thus, at the time of absence of the signal Request and the presence of the signal N. Ust. the information inputs of the comparison circuit 9 have the same zero codes and

5 0 5 0 5

0

5

0 5

its output is high. The enable signal from the output of the comparison circuit 9 is fed to the second input of the And element 2. The clock frequency from the synchronization circuit common to devices of all channels is fed to the first input of this. The clock frequency from the output of the element And 2 goes to the sync input of the shift register 1 and to the input of the blocked delay element 5. In addition, through the delay element 3, the clock frequency is supplied to the clock input of counter 6. After the signal is received, N. Set. counter 6 will change its state with the arrival of each clock pulse from zero to the n-th, where n is determined by the maximum value of the number of bits of the priority code. The priority code is entered into shift register 1 in the silent mode. Request. Counter b is in cyclic mode. Counter 10, in the absence of a signal, the Request is held in the zero state. Thus, at the output of the comparison circuit 9, once per cycle of operation of the counter b, an enable signal for the And 2 element will appear. This will continue until there is no Request signal, i.e. on bus 19 low potential. In addition, the potential on the request bus 19 holds the second trigger 14 in the zero state and through the And 13 element the first trigger 11.

When a Request signal is received in several devices, the counter 10 of these devices is unlocked. In addition, the first trigger 11, the second trigger 14, the delay element 5, the main amplifier 7, as well as the shift register 1, are switched to the cyclic shift mode. At the time of switching, the cyclically working counter 6 to the zero state from its output to the first input of the And 2 element, the resolving potential comes in. Thus, at this moment the clock pulse goes through the And 2 element to the sync input of the shift register 1 and through the unlocked delay element 5 to counter clock input 10 and gate input of comparison circuit 8.

1 The leading edge of the code that determines the priority of the device appears along the leading edge of the clock pulse at the output of the shift register 1. The signal from the output of the shift register through the unlocked main amplifier 4 is fed to the common highway 17. At the same time, the resulting potential (mounting I) is established on the common highway, which is fed to the first input of the comparison circuit 8 through the main amplifier 7. A signal is received at the second input of the comparison circuit 8 from the output of the shift register 1.

The comparison occurs at a high level of the clock pulse supplied to the gate input of the comparison circuit 8 through a delay element 5, which compensates for the transient time, the establishment of the resulting potential on the common highway 17 and the delay of the main amplifiers 4.7. A counter 10 is triggered on the trailing edge of the clock pulse and changes its state. Counter b, just like counter 10, will change state along the trailing edge of a clock pulse generated at the output of delay element 3. The delay time of the clock pulse by the delay element 3 is determined by the total transit time of the clock pulse through the AND element 2 and the delay element 5. Thus, the counters 6 and 10 will synchronously change their state and at the output of the comparison circuit 9, the resolving potential for the element And 2 will be maintained, and in the comparison circuit 8, priority codes will be sequentially compared, starting with the oldest (bit).

If at the time of comparison the first input of the comparison circuit 8 has a low potential, and the second input (the output of the shift register) has a high potential, which indicates the presence of a higher priority subscriber on the trunk, then a positive difference is formed at the output of the comparison circuit 8, by which trigger 11 | is set to a single state. In this case, the low potential from the inverse {output of the trigger 11 through the And element 12 switches the shift register 1 to the parallel information recording mode, blocks the delay element 5, the main amplifiers 7, and sets the counter 10 to its initial (zero) state. Thus, this device is excluded from arbitration. If the device has the highest priority, then after performing all the comparison cycles at the output of the overflow of the counter 10, a positive differential will appear, which goes to the clock input of the trigger 14 and sets it to the single state. Low potential with inverse trigger 14 output through trunk | amplifier 4 goes to the common highway j 17 and to output 20 Confirmation of capture, informing the subscriber about permission to work with | shared resource

 At the output of the pulse generator 15 (all devices form a low potential, allowing the counter 16 to work. After a period of time determined by the conversion factor of the counter 16 and equal to the transmission time interval of the smallest possible information array, the output of the overflow of the counter 16 is negative potential, which through the elements And 12, And 13 sets the device to its initial state. After the signal is received, the Request trigger 14 in the device that has captured the shared resource is returned to its original state. line 17 low potential is removed

and the arbitration session is repeated. For each positive edge on the general highway 17 in arbitration mode, the pulse shaper 15 generates positive null pulses

counter 16.

One of the possible options for constructing the proposed device is the use of a microcircuit: shift register - 133IR13; comparison schemes - 133SP1; counters - 133IE5; triggers - 133TM2; the pulse shaper and delay elements are made on 133TM2; trunk amplifiers and elements I-133LAZ, LA4, LAV. .. The use of this device allows arbitration of requests to capture a shared resource when implementing persistent access methods with the exception of the influence of the arbitration time on the time a subscriber takes a shared resource

and indication of the moment of capture of the shared resource.

Claims (1)

SUMMARY OF THE INVENTION A multi-channel device for connecting subscribers to a shared resource, comprising channels, each of which contains a shift register, a first circuit. comparisons, two triggers, three counters, two elements And with each channel input the channel priority code is connected to the shift register information input, the device channel request input is connected to the first input of the first AND element, the second input of which is connected to the inverse output of the first trigger, characterized in that. in order to expand the scope of the device by indicating the end of the arbitration, a third AND element is additionally introduced into each channel. a second comparison circuit, two main amplifiers, two delay elements and a pulse shaper, wherein in each channel the request channel of the device channel is connected to the first input of the second element And and the installation information input of the second trigger, the inverse output of which is connected to the blocking input of the first main amplifier and is confirmation channel output of the device, the initial installation input of which connected to the reset input of the first counter, the output of which is connected to the first input of the first comparison circuit, the second input of which is connected to the information output of the second counter, the overflow output of which is connected to the sync input of the second trigger, the output is equal to the first comparison circuit connected to the first input of the third element And, the output which is connected to the sync input of the shift register and the sync input of the first delay element, the output of which is connected to the counting input of the second counter and the gate input of the second comparison circuit the output of which is connected to the sync input of the first trigger, the installation input of which is connected to the output of the second element And, the second input of which is connected to the overflow output of the third counter and the third input of the first element And, the output of which is connected to the reset input of the second counter, the lock input of the first delay element and the control input of the shift register, the output of which is connected to the information input of the first main amplifier and the first information the input of the second comparison circuit, the second information input of which is connected to the output of the second main amplifier, the blocking input of which is connected to the output of the first element And, clock the channel input of the device is connected to the counting input of the third counter, the second input of the third And element and through the second delay element to the counting input of the first counter, the output of the driver pulses connected to the reset input of the third counter, the outputs of the first main amplifiers of all channels of the device are combined via MOUNTING OR and connected to the information inputs second trunk amplifiers and pulse shaper inputs of all device channels. FIG. 1 Reda hysterical Compiled by B. Toothless,. Tehred M. Morgenthal Corrector M. Weaver Zach J3 2866 Circulation VNIIIPI of the State Committee for Inventions and Discover at the USSR State Committee for Science and Technology 113035, Moscow, Zh-35, Rauska nab., 4/5 Fie.Z Subscription