SU847320A1 - Priority device - Google Patents

Description

one

The invention relates to computing and can be used in the organization of exchange between peripheral devices.

A priority device is known that contains random logical nodes and the elements AND, OR, AND-NOT G1.

However, such a device does not allow changing the established order of polling information sources.

Priority device is known. containing two registers, control unit, AND, OR G21 elements.

The disadvantage of such a device is that with a large number of subscribers, the connection time of lower priority subscribers is significantly increased.

The purpose of the invention is to expand the functionality.

The goal is achieved in that a priority device containing two n-bit registers, a group of AND elements and a control unit containing the first AND element, the first OR element, a shift register, the single inputs of the first register triggers and With the corresponding inputs of the first element OR of the control unit, the single output of the trigger of each bit of the first register is connected to the first. the input of the corresponding element AND of the group, the second input of each element AND of the first register is connected to the corresponding output of the shift register of the control unit, the output of each element AND of the group is connected to the single input of the corresponding trigger of the second register, the single output of each trigger of the second register is connected to the corresponding output of the device, zero output each trigger of the second register is connected to the corresponding input of the first element AND of the control unit; the second element is entered into the control unit the third element OR, the mode trigger, the control trigger, the outputs of the elements and the group are connected to the corresponding inputs of the second OR element of the control unit and the zero inputs of the corresponding triggers of the first register, the output of the second OR element of the control unit is connected to the zero input of the control trigger, with the first input of the second element And the control unit,

the control input of the device is connected to the corresponding input of the first OR element of the control unit and the zero inputs of the second register triggers, the clock input of the device is connected to the clock input of the shift register, the control input of the shift register is connected to the output of the control trigger, the reset input of the shift register is connected to the third output the OR element of the control unit, the mode input of the device is connected to the single input of the mode trigger, the output of the mode trigger is connected to the second input of the second element AND block control, the output of the second element AND control unit is connected to the first inputs of the third OR element of the control unit, the second input of the third OR element of the control unit is connected to the last output of the shift register, the output of the first OR element of the control unit is connected to the corresponding input of the first AND element of the control unit.

Diagram of the device shown in the drawing.

The circuit contains the first register 1, the second register 2, the control block 3, the triggers 4 of the first register, the elements and 5 of the first register, the triggers of the second register 6, the shift register 7, the elements OR 8-10, the elements 11.11, the trigger 13 control trigger 14 modes, inquiry inputs 1-5 of the device, control input 16, clock input 17, device outputs 18, input .19 modes.

The priority device operates as follows.

The device works in two modes. The modes of operation of the device are determined by the state of the triggers 14 of the mode. At zero state of the trigger

14 (in the sequential polling mode), after the withdrawal of the service request for the outgoing subscriber, the polling signal propagates to the next channel connected to the lower priority subscriber.

With a single state of trigger 14 (in the priority polling mode), after the service request of the old subscriber is removed, the polling begins the channel connected to the subscriber with the highest priority. In both modes, the priority of the channels is determined by their order, i.e. The first channel has the highest priority.

When prompted to enter

15 devices, the corresponding triggers 4 of register 1 are set to a single state and through the elements of OR 8, AND 11 are set to a single state trigger 13 and at its single output generates the potential that goes to

the control input of the shift register 7, and upon receipt of the clock pulses at the clock input 17 of the device, the outputs of the shift register 7 are generated. sa They arrive at the inputs of elements of the L 5 register 1. If the trigger 4 of the register 1 is in the single state, then the output of the element 5 will be a signal that will form fl on the single output of the trigger 6

 register 2 is a permission signal for servicing a subscriber connected to input 15 of the device. At the same time, at the zero input of the trigger 13, a signal appears through the OR element 9

5 which resets the trigger to the zero state. The control signal / arriving at the control input of the shift register 7 is removed. The generation of signals at its outputs is stopped and interrogation of the register 1 is stopped. In the sequential service mode, the trigger 14 is in the zero state. After the termination of the service, the trigger 6 is reset by the signal from control input 16 and the service enable signal is removed. At the same time, the element OR 8 flip-flop 13 sets Qs to one, the shift register 7 is started and the next trigger flush of register 1 is polled. When the polling signal is generated at the last output of the shift register 7, then through the OR element 10 it goes to the input Reset the shift register 7 .and returns it to its original state.

in the priority service mode, the trigger 14 modes is set to one. From the single output of this trigger, the input of the And 12 element is allowed to pass a signal from the OR 9 element, which resets

the shift register .7 to the initial state, i.e. after the subscriber service has finished, the polling will start again from the first higher priority channel.

The application of the proposed invention allows the device to expand its functionality by introducing sequential and priority polling modes of subscribers using a trigger.

Claims (2)

1. USSR author's certificate 0 No. 474807, cl. G 06 F 9/18, 1976. 2. USSR author's certificate number 600557, cl. 6 06 F 9 / 18,1978 (prototype).