SU1536381A1 - Cyclic priority device - Google Patents

Abstract

The invention relates to computing and can be used in computing systems. The purpose of the invention is to increase speed. The device contains two registers, a prohibition element, triggers, NOT elements, AND elements and OR elements. The device searches for a subgroup of sources of the application in which there is a request, and then finds the request in the subgroup. 1 il.

Description

The invention relates to computing and can be used in computing systems.

The aim of the invention is to improve the speed of the device.

The drawing shows a diagram of the device.

The device contains registers 1 and 2, elements AND 3, element OR 4, prohibition element 5, triggers 6, shift registers 7, elements OR 8. and 9, elements 10 and 11, elements NOT 12, device clock input 13, input 14 device startup, request inputs 15 devices ,, outputs 16 devices, trigger 17.

The device works as follows.

When the power is turned on, the registers 1 and 2 are zeroed, the trigger 17 is set to one, the first trigger 6 is set to one, the registers 7 are set to zero (the circuit for setting the registers and triggers is not shown). Later recorded in the first trigger 6 1 is cyclically shifted by the triggers 6 and the registers 7. After that, the clock pulses begin to arrive at the input 13. They pass through the open prohibition element 5 and shift 1 into triggers 6 and registers 7. Requests from subscribers are received at inputs 15 and are written to the corresponding bits of register 2.

If there are no requests in the subgroup of register 2 bits, then the output of the element OR 8 connected to the outputs of the bits of register 2 of this subgroup will have a zero potential that is inverted through the element connected to it. NO 12 and opens the element AND P. As a result, 1 from the output of the first trigger 6 is rewritten through the element OR 9 to the second trigger 6.

If in the subgroup of register bits 2 there is at least one request, then at the output of the element OR 8 connected to the outputs of the register bits

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2 of this subgroup, there will be a single potential that opens the element AND 10 connected to the output of the element OR 8. As a result, 1 from the output of the first trigger 6 is written to the register 7 of this subgroup and will move until the subscriber in the subgroup from which the request came. If at the moment there are 1 in the same triggers 6 and the corresponding registers 2 and 7, then the output of the corresponding element And 3 appears to be a single level, with the result that the corresponding register register 1 is set to one and a signal appears at the output 16, allowing the subscriber to establish communication with the server. In addition, a single level appears at the output of the element OR 4, as a result of which the prohibition element 5 closes (the shift 1 in the triggers | and registers 7 is temporarily stopped), and the trigger 1 7 is set to the zero state, the potential recording is blocked by the block from the outputs of the AND 3 elements into the register 1. The unit level from the output of the discharge of the register 1 zeroes the corresponding discharge of the register 2. As a result, the single potential from the output of the element AND 3, and consequently, from the output of the element OR 4, is removed, as a result which again begins a shift of three gag registers 7. This will search for the next service request.

If a request is found in some bit of a subgroup of register bits 2 that has requests, then a single potential appears at the output of the corresponding AND 3 element, which closes the prohibition element 5 and confirms the zero state of the trigger 17, the contents of register 1 does not change, since writing to it is blocked. The device is placed in a state of waiting for service of the next request.

If the next request is not found during the maintenance of the next request, the device is not in the idle state and the cyclic shift 1 is triggered.

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herah 6 and registers 7 to detect the query.

After the end of the service of the next request, a pulse is applied to the input 14, which sets the trigger 17 to one state. In this case, the register bit 1 is zeroed out, and if the device has been transferred to the idle state, the next bit of the same register is set to one.

Claims (1)

Invention Formula A cyclic priority device containing the first shift register, two registers, the group of elements AND, the first element OR, the first trigger and the prohibition element, whose direct input is connected to the clock input of the device, the inverse input of the prohibition element is connected to the output of the OR element whose inputs are connected with the outputs of the corresponding AND elements of the group and the corresponding information inputs of the first register, the outputs of which are the outputs of the device and connected to the zero inputs of the second register, the single inputs of which are united with the device's request inputs, the outputs of the second register are connected to the first inputs of the AND elements of the first group, the device request input is connected to the single input of the first trigger, the zero input of which is connected to the output of the OR element, the output of the first trigger is connected to the synchronization input of the first register, the prohibition element output connected to the synchronization input of the first shift register; the outputs of the first shift register, except for the last output, are connected to the second inputs of the corresponding AND elements of the group, starting with the second And, characterized by the fact that, in order to improve speed, the second and third triggers are introduced into it, the four elements are AND, the second, the third, the fourth and the fifth elements are OR, two elements are NOT and the second shift register, and the first group of outputs of the second the register is connected to the inputs of the second element OR, the output of which is connected to the first input of the first element AND, and through the first element HF to the first input of the second element AND, the second 1515 151515 G5 15 ffiffl