SU1566350A1 - Priority device - Google Patents

Abstract

The invention relates to computing, in particular to information exchange control devices, and can be used for access of several sources to a common resource. The purpose of the invention is to expand the field of application of the device by enabling it to work in systems of exchange with a common resource, the exchange cycle with which consists of two operations. The device contains priority block 14, and in each channel 1 there are OR elements 2, 5, 13, triggers 3, 4, 6, 10, 12, delay elements 7, 8, elements AND 9, 11. The invention allows to create multimicroprocessor systems with a shared memory resource by introducing a priority scheme into the device. In this case, requests are served not according to a hard priority, but as they arrive. In this case, interrogation signals distributed in time are formed at the output, which makes it possible to eliminate the triggering of two or more channels simultaneously. 1 hp f-ly, 2 ill.

Description

The invention relates to computer technology, in particular, to information exchange control devices, and can be used to dog several sources to a common resource.

The purpose of the invention is to expand the field of application of the device by enabling it to work in systems of exchange with a common resource, the exchange cycle with which consists of two operations.

Figure 1 shows a diagram of the device priority; FIG. 2 is a priority block diagram.

The priority device contains channels 1, containing each element AND-OR 2 triggers 3 and 4, element OR 5, trigger 6, elements 7 and 8 of the delay, element And ° 9, trigger 10, element 11, trigger 12, the element OR 13. The device also contains a priority block 14, request inputs 15, initial setup inputs 16, start inputs 17, response inputs 18, polling inputs 19, write enable inputs 20, outputs 21, and clock inputs 22 and 23.

The priority block contains transmitters 24, element 25, receiver 26, trigger 27, element AND 28, decoder 30,

The priority device operates as follows.

In the initial state, after turning on the power, the initial set signal supplied to the device inputs 16 triggers 3,4,6,10 and 12 are set to the zero state. Since the trigger 12 is set to the zero state, the outputs of the transmitters 24 of the priority block in the output state are in the one state. At the inputs 22 and 23 of the device there are clock frequencies. At the information input of the trigger 27, in the initial state, there is a logical zero, which means that the locking trigger 27 is also in the zero state. This leads to the fact that at the output of the element IS-NOT 28 there is a clock frequency from input 22, since at the first input of the element IS-NOT 28 there is a signal from the inverse output of the trigger 27, Thus, in the initial state at the outputs of the priority block 14 Channel 1 polling signals are present.

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Suppose that at the same time a request signal arrives to two channels (at the inputs 15 of the device).

Requests are sent to the setup input of trigger 6. Thus, two triggers 6 in the channels are set by the request signals to one state. Logic unit must be fed to inputs 17. Then, on the leading edge of the polling signal from the first output of the decoder 30, first the trigger 12 of the first channel is set to one.

After the trigger 12 of the first channel is set to one, the logical one is set up at the information input of the trigger 27, and then, according to the clock frequency signal from the output of the element 25, the trigger 27 is set to one. The inverse output of the trigger 27 prohibits the passage of the clock frequency to the output of the AND-NE element 28, which means that a single state is established at the corresponding output of the block 14, and the counter 29 is set to the next state. After that, the corresponding output 21 is signaled to enable operation with a shared resource.

At the end of the execution of each function at the input 18 there is a signal about the completion of the function.

The trigger 10 is set to one. This state is only after the completion of the second function, since the trigger 3 is set to one state only after the arrival of the signal from input 19.

After the trigger 10 is set to one, a pulse is generated at the output of the element 11 and a pulse through the element OR 13 at the reset input of the flip-flops 12. The triggers 12 and 3 of the first channel are set to zero. At the clock frequency, the trigger 27 is set to zero, since the first one has a logical zero. Thereafter, a pulse is formed at the second output of the block 14, which now sets the trigger 12 of the second channel to one state. Next, the device works the same

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Claims (2)

1. A priority device containing a priority block, channels, and in each cable - two flip-flops and two AND elements, with each request input of the device connected to a single trigger input of the same channel, the direct outputs of the channel flip-flops are connected to the information input of the priority block, each output of the group the outputs of which are connected to the first input of the first element AND of the channel of the same name, the output of the first element AND of each channel is connected to the clock input of the second trigger of its channel, characterized in that, in order to expand the application of the device by enabling it to work in systems of exchange with a common resource, the exchange cycle with which consists of two operations, the device contains in each channel the third, fourth, fifth triggers, two delay elements, and three OR elements, and the inverse output of the second trigger in each channel is connected through the first delay element ten 15 20 25 The first element of the first third channel to the channel is connected to the device's input of the same name, the third and fourth units of each three channels are connected, respectively, to the input input of the recording resolution of the same name, the second input of the first channel element is connected to the same channel start up the device, one turn of the first trigger is connected to the single input of the trigger of its channel, the upper channel triggers are the device, the first and second inputs of the device are connected to the first and second inputs of the unit howl input of the first trigger with the output of the first element AND channel. 2. The device according to claim 1, that the block n contains a group of transmitters nick, trigger, element I, and with the first input of the first element OR, 30 counter and descrambler, the second input of which is connected to the same input of the initial installation of the device and the first input of the second OR element of its channel, the output of which is connected to the reset inputs of the second, third and fourth triggers of its channel, the outputs of which are connected respectively to the first and second inputs of the third OR element of its channel, the output of which through the second delay element is connected to the first input of the second element AND of its channel, the output of which is connected to the second input of the second element OR of its channel, the second input of the second lementa and connected to the output of the fifth flip-flop its channel, the single input of which is connected to the output per0 five 0 five the zero element of the first channel is connected to the device of the same name as the cotton input device, the units of the third and fourth triggers of each channel are connected to the same input of the poll and the recording input device, the second input of the first element AND of each channel is connected to the same launch input of the device, the unit output of the first trigger of each channel is connected to the single input of the second trigger of its channel, the outputs of the second channel trigger are output s device, the first and second clock inputs of the device are connected respectively to the first and second clock inputs of the block priority, radiation input of the first flip-flop connected to the output of first OR cRoeio channel. 2. The device according to claim 1, that is, that the priority block L contains a group of transmitters, a receiver, a trigger, an I element, an energy input. exits five 0 5 of which are bpokl outputs, the inputs of which are connected to the transmitter inputs of the group, the outputs of which are combined and connected to the inputs of the receiver, the output of which is connected to the single input of a trigger, the output connected to the first input of the NAND element, the output of which is connected to the counting input of the counter and r control input of the decoder, the information inputs of which are connected to the outputs of the counter, the first and second clock inputs of the block are connected r the first and second inputs of the element I, the output of which is connected to the reset input of the trigger , the first Spock input is connected to the second input of the NAND element. fig 2