SU610301A1 - Pulse distributor - Google Patents

Description

PULSE DISTRIBUTOR

(54)

I

The invention relates to devices for pulsed technology and can be used to build pulse distributors.

Pulse distributors are known, in which at least three elements per bit l are used to realize one output.

Their disadvantage is povashhenna complexity

Also known is a pulse distributor, which contains in each discharge a trigger on two AND-NOT elements and two output IS-NOT elements, outputs with odd numbers of the distributor are connected to the outputs of the first output AND-NOT elements, and outputs with an odd-numbered pin and - From the output 1 mi of the second output elements NAND, the input of the initial installation of the pulse distributor is connected to the input of the second element NAND trigger of the first bit C2.

The disadvantage of the transducer is its narrow functionality.

The purpose of the invention is to expand the functionality of the pulse distributor,

This goal is achieved by the fact that in the pulse distributor, which contains a trigger on two elements AND-NOT and two output elements AND-NOT in the hygdroid discharge, the outputs with odd 1.1.1 and the distributor numbers are connected to the outputs of the first output elements AND-NOT, and the outputs with even numbers - with the outputs of the second output elements of the NAND, the input of the initial installation of the pulse distributor is connected to the input of the second element of the NAND trigger of the first bit, the output of the first element of the NAND trigger of the nth bit is connected to the inputs of the second AND NAND trigger (n + 1) -r bit and the first element IS-NOT trigger (t + 2) -th bit, and the output of the first element IS-NOT trigger the penultimate bit connected to the inputs of the second element AND-NOT trigger the last bit and the first element IS-NOT trigger the first bit, and the output of the first element of the NAND trigger of the last bit is connected to the inputs of the second element AND of the NAND trigger of the first bit and the first element of the NAND trigger of the second bit, the inputs of the first output element of the N – N of the nth bit are connected with the outputs of the second elements AND-NOT triggers etogs and (n + 2) -th ASP rows, wherein E; {ols first output of AND-NO penultimate discharge connected to the output

of the second element of the first NI of the trigger of this and the first bit, and the inputs of the first output element of the NAND of the last bit — with the outputs of the second element of the N – N flip-flops of this and the second bit, the inputs of the second output element of the N-N The first bit is connected to the outputs of the first AND elements of the NAND triggers of this and (T1H-2) th bits and to the output of the second element of the AND – HY trigger (n + I, and the inputs of the second output element of the NAND of the second last digit connected to the outputs of the first elements of the AND-NOT triggers of this and the first bit and to the output of the second The AND-NOT trigger of the last bit and the inputs of the second output AND-NOT of the last digit to the outputs of the first AND-NOT elements of this and the second bit and to the output of the second AND-NO element of the first bit, the first clock bus The pulses are connected to the inputs of the first elements. AND-NOT triggers of odd bits, and the second bus clock pulses - to the inputs of the first elements AND-NOT triggers of even bits.

The drawing shows a functional distribution circuit for 12 channels.

The distributor contains triggers on the elements AND-NOT: 1i2, Zi4, 5i b, 7 and 8, 9 and 10, 11 and 12 of the first, second, third, fourth, fifth and sixth bits, respectively, output elements 13-24, tires 25 and 26 clock pulses and bus 27 of the original installation.

Bus 25 clock pulses connected to the inputs of the first elements of the odd trigger, that is, to the inputs of elements 1.5 and 9. Bus 26 is connected to the inputs of the first Elements of even trigger, that is, to the inputs of elements 3, 7, 11.

The output of the first element of each trigger is connected to the inputs of the second element, n «- 1 trigger and the first element of the trigger, and the first one follows the last trigger when counting. So the output of element 1 is connected to the inputs of elements 4 and 5. The output of element 3 is connected to the inputs of elements 6 and 7. The output of element 9 is connected to the input of element 12 and, since the last trigger follows the first trigger, to the input of element 1.

The inputs of each of the odd output elements are connected to the outputs of the second elements of Pi and ri + 2 flip-flops. The inputs of the element 13 are connected to the outputs of the elements 2 and 6.. The inputs of the element 15 to the outputs of the elements 4 and 8, etc.

The inputs of each of the even output elements are connected to the output of the second element g + 1 flip-flop and the outputs of the first elements 51 and l + 2 flip-flop. The inputs of the element 14 are connected to the outputs of the elements 4, 1, 5; the inputs of the element 16 to the outputs of the elements 3, 6, 7; "Moves element 18 - to the outputs of the elements 5, 8, 9, etc. Bus 27 serves to set the initial state of the distributor.

The distributor works as follows.

At the initial moment of time, the circuit is with high potentials at the outputs of elements 2, 4, 5, 6, 7. 9-11-24 and with low potentials at the outputs of the remaining elements, i.e. The triggers on elements 1-4 are in the state, the triggers on elements 7-12 are in the state O, and the triggers on elements 5 and 6 are in the state with high potentials at the outputs of both arms, which we denote

I I 9 1

 .

The next moment, the first clock pulse arrives on bus 25, which causes the appearance of high potential at the output of element 1. It should be noted that, in the scheme, the elements AND are NOT for positive signals at the input.

High potential from the output of element 1 enters the inputs of elements 2 and 14 and causes a low potential at their outputs at a certain moment.

Thus, the first trigger on elements 1 and 2 is in the o state. the potential from the output of element 2 enters the input element

5 13 and causes a high potential at its output at another moment. Next moment on the bus 25 appears a positive potential and at the output of the element 5 there is a low potential, since at all its inputs there are high potentials, the third trigger of the pulse distributor i.e. the trigger on elements 5 and 6 is in the state. The low potential from the output of element 5 enters the input of element 8 and sets the fourth state to 2 and so on. d.

Thus, in the circuit circulate

0 the following trigger states:

112,000

011200

001120

000112

five

200011

120001

112,000

The outputs of elements 13-24 are removed.

60 negative distributor output signals.

Claims (2)

If it is necessary to obtain positive output signals, fi5 element Hi should be used as output elements. Impulse distributor, containing in each discharge a trigger on two AND-NOT elements and two output elements, and-НЁ, the outputs with odd numbers of the distributor are connected to the outputs of the first output elements AND-NOT, and outputs with even numbers - with the outputs of the second output elements AND-NOT, the input of the initial installation of the pulse distributor with the input of the second element AND-NOT of the first discharge trigger, is different In order to extend the functionality, the output of the first NAND trigger element of the nth digit is connected to the inputs of the second AND NAND trigger element (n + 1) -th bit and the first AND-NOT trigger element ( n + 2) -th bit, with the output of the first AND-NOT trigger element and the last-last bit connected to the inputs of the second AND-NOT trigger element of the last bit and the first AND-NE element of the first bit, and the output of the first INE element the last bit trigger is connected to the inputs of the second INE element of the first bit trigger a and the first element of the NAND trigger a second time row, the inputs of the first output element of the NAND, G1th bit are connected to the outputs of the second NAND element of this and (n + 2) -th bit triggers, and the inputs of the first the output element of the IS-NOT of the last-but-one bit of the connection with the outputs of the second elements of the IS-NO trigger of this and the first bit, and the inputs of the first output element of the INE of the last bit — with the outputs of the second element of the IS-NE of the triggers of this and the second bit output element. The NAND of the nth digit is connected to the outputs of the first elements of the NAND triggers of this and the (l + 2) th bits and to the output of the second element of the NAND trigger (n + 1) of the second bits, and the inputs of the second the output element of the NIP of the last but one bit is connected to the outputs of the first AND elements of the NAND triggers of this and the first bit and to the output of the second element of the NAND trigger of the last bit, and the inputs of the second output element of the NAND of the last bit to the outputs of the first And-NOT elements of the triggers of this and the second bit and to the output of the second element and-NOT of the first p trigger sp yes, the first bus is connected to the clock inputs of first AND-NO elements flops of odd bits, and the second bus clock - pervyh- to inputs of AND-NO elements even bits triggers. Sources of information taken into account during the examination: 1.Bukreev I.N. and others. Microelectronic circuits of digital devices. M., Soviet Radio, 1975, p. 293, fig. 6.25. 2.Bukreev I.N. et al. Microelectronic circuits of digital devices. M., Soviet Radio, 1975, p. 294. FIG. b. 26 L piece Ul4jl ll w fff