SU671034A1 - Pulse frequency divider by seven - Google Patents

Description

one

The invention relates to a pulse technique.

A known frequency divider containing p flip-flops, a source of input pulses, a unit for generating complementary pulses, logic gates And intended for transmitting signals from the outputs of flip-flops to inputs 1.

The disadvantage of such a divider is the limited frequency range.

The closest in technical essence to the claimed is a frequency divider containing triggers made on OR-NOT gates, the inputs of which are connected to the gates of gates AND, the block of forbidden gates determining the frequency division factor, amplifiers and drivers elements and bits are connected to the corresponding outputs of the trigger bits of the divider 2.

The disadvantage of this divider is low reliability.

The purpose of the invention is to increase the reliability of the divider.

The proposed divider contains five triggers performed on the OR-NOT logical elements, the inputs of each of which are connected to the outputs of the logical elements I. The first inputs of the logical elements AND of the first discharge are connected to the direct and inverse outputs of the fourth discharge trigger. elements of the second bit - with direct and inverse outputs of the trigger of the same bit. The first inputs of logic gates of the third and third bits are connected with the direct and inverse outputs of the fourth bit trigger, the first inputs of the logical elements of the fourth and fourth gates are connected with the direct and inverse outputs of the third discharge trigger, and the first inputs of the logic elements of yes - with direct and inverse triggers of the second bit.

A distinctive feature of the proposed divider is that a logical element NOT and an additional logical element AND are inputted into it, the output of which is connected to an additional trigger input of the fifth digit, the second inputs of the logical elements AND of the first digit being connected to one of the trigger inputs of the second digit , the second input of one of the logical elements AND the second bit - with the input width and the second inputs of the logical elements AND the third bit, and the second input of the second logical element AND the second bit - with one of the trigger inputs Dr third discharge. The second inputs of logical elements And

the fourth bit is connected to the second inputs of one main and additional logic elements And the nth bit and the output of the logical element NOT, the input of which is connected to the input bus, the second input of the second logic element and the nth bit - to one input of the fourth trigger , and the inputs of the additional logical element I - to the direct outputs of the first and second bit triggers. An additional input of the first logical element AND of the third bit is connected to the inverse output of the trigger of the fifth bit.

The structural electrical circuit of the described frequency divider is shown in the drawing.

The frequency divider contains triggers 1-5, performed on the logical elements OR NOT 6-15, logical elements AND 16-26, the logical element is NOT 27.

The input signal is fed to the input bus 28, the output signal is removed from the output 29.

The principle of operation of the divider is as follows.

When the first pulse arrives, a single potential appears at the input bus 28 of the device, and the third trigger changes its state. Then, a single potential is formed at the output of the logical element 27, and the fourth trigger changes its state.

With the arrival of the second pulse, a single potential appears at the input bus of the device, and the second trigger changes its state. The third trigger returns to its original state. Then there is a negative potential at the output of the logical element 27, and the fourth trigger is set to its initial position.

When the third pulse arrives, a single potential appears at the beginning on the device input bus, and the third trigger changes its state.

Then there is a single potential at the output of the He 27 logical element, and the fourth and fifth triggers change their state.

With the arrival of the fourth pulse, a single potential at the device input bus 28 first appears, and the second and third triggers return to their original positions, and the first trigger changes its state. Then a single potential appears at the input of the NOT 27 logical element, and the fourth and fifth triggers are reset.

When the fifth pulse arrives, a single potential is first formed on the device input bus, and the third trigger changes its state. Next, a single potential appears at the output of the He 27 logical element, and the fourth trigger changes its state. With the arrival of the sixth pulse, the unit potential at the input bus of the device first appears, and the second trigger changes its state, and the third trigger returns to the initial state.

Thereafter, a single potential is formed at the output of the He 27 logical element, and the fourth trigger returns to its original position, and the fifth trigger changes its state.

When the seventh pulse arrives, a single potential appears at the beginning on the device input bus, and the first and second triggers occupy the initial state, with

this turns out to be a single potential at the output of the device. Then, a single potential at the output of the logical element NOT appears, and the fifth trigger returns to its original state. Sun scheme takes

initial position.

Claims (2)

1. US patent number 3943379, CL. 307-225, pub. 1976. 2. For the Japan of Japan L 49-32621, cl. 98/5 s / 32, 1974.