SU1644146A1 - Device for checking a serial binary code - Google Patents

Description

(21) 4711930/24

(22) 04.24.89

(46) 04.23.91. Bul № 15 (72) A.N. Novikov

(53) 681.3 (088.8)

(56) USSR Author's Certificate V 530332, cl. G 06 F 11/10, 1974.

USSR Author's Certificate V 1319036, cl. G 06 F 11/10, 1986.

(54) DEVICE TO CONTROL A SEQUENTIAL BINARY CODE

(57) The invention relates to automation and computing and can be used in discrete communication devices. The purpose of the invention is to reduce the device equipment.

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The received information is fed to the counting input of trigger 1. According to the clock signals generated at the end of the received word, the contents of trigger 1 are recorded in a two-bit shift register 3 and, through element 2, enter the input of delay element 4. The output of shift register 3 is gated on the AND element 6 by a clock signal delayed by the delay element 4. Comparison node 7 compares the signals from the outputs of the element 6 and the delay element 5. With an even number of units, a zero signal is present in the received word at the output of the comparison node 7, and for odd - single. 2 Il.

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The invention relates to automation and computing and can be used in discrete communication devices.

The aim of the invention is to reduce the hardware of the device.

Figure 1 shows the functional diagram of the device; figure 2 - the timing diagram of his work.

The device contains a trigger 1, the first element And 2, the shift register 3, the delay elements 4, 5, the second element 6 and the comparison node 7.

The device works as follows.

Before starting work, the installation input II of the device sends a signal and sets the trigger G and the shift register 3 to zero states. On, figa

As an example, such a code is presented in words, six bits each. The trigger 1 generates the output binary sequence (see figv). Pulses with a frequency of binary words, combined in time with the last digit of the word, are applied to the clock input III of the device (Fig. 26). Fig. 2d shows the output states of trigger 1 in the form of zeros and ones that have passed through the element 2. These states are tied in time to the last bit of each binary word being tested. In Fig. 2c, these same states are represented, but delayed, as well as 3 shifts extended by the register for one period of the impulses of binary words. Comparison node 7 summarizes

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Liu two logical values presented in fig.2d, and. Figure 2k shows the results of these additions, which coincide in time with the first digit of the next word. Modulo two addition results are the results of parity checks for binary words.

In Fig. 2a, binary words are numbered in Arabic numerals; in Fig. 2k, the corresponding parity values of these words are delayed for the duration of one bit.

Trigger 1 is set to the zero state once - before starting work. At its output, along with even values, there can be odd ones, with an odd number of logical units in a word. In the latter case, the verification of the next binary word begins when trigger 1 has a state of logical one. Addition modulo two logical states of trigger 1 for checking the previous and current words is the result of the parity of the current word. For example, if the previous word was odd, i.e. trigger 1 is set to the state of logical one, then with an even number of logical units in the current word, state of trigger 1 remains the same, and the result of addition modulo two will be equal to zero.

For normal operation of the device, the shift register 3 is chosen two-bit. In order for the trigger 1 to transfer, the information in register 3 is shifted along the trailing edge of the pulse. Delay elements 4 and 5 have a signal delay time equal to the duration of one bit.

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words and provide a comparison by the node 7 test bits at the outputs of the element AND 2 and the delay element 4. With At the output of the comparison node 7, a parity signal of the received information words is generated.

Formula

the invention

A device for controlling a serial binary code containing a trigger, two AND elements, a first delay element and a comparison node, the counting and installation inputs of a trigger are connected to the information and installation inputs of the device, respectively, the output of the trigger is connected to the first input device through the first delay element connected to the first input of the second element AND, the output of which is connected to the first information input of the comparison node, the output of the inequality of which is output ode device, about t - distinctively, in order to reduce the equipment of the device, it contains a shift register and a second delay element, and the trigger output is connected to the information input of the shift register, the output of the last bit of which is connected to the second input of the second element , the setup input of the shift register is connected to the setup input of the device, the clock input of the device is connected to the clock input of the shift register and the second input of the first And element, the output of which is connected to the second through the second delay element m information input node

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Claims (1)

Claim A device for monitoring a serial binary code containing a trigger, two And elements, a first delay element and a comparison node, and the counting and installation inputs of the trigger are connected to the information and installation inputs of the device, respectively, the output of the trigger is connected to the first input of the first element And, the clock input of the device through the first delay element is connected to the first input of the second element And, the output of which is connected to the first information input of the comparison node, the inequality output of which is the output device, characterized in that, in order to reduce the equipment of the device, it contains a shift register and a second delay element, and the output of the trigger is connected to the information input of the shift register, the output of the last discharge of which is connected to the second input of the second element And the installation input of the shift register 35 is connected to the installation input of the device, the clock input of the device is connected to the clock input of the shift register and the second input of the first AND element, the output of which through the second 40 delay element is connected to the second by the input of the comparison node. f "". / ' ^{2 J} * 5 even Chet odd odd even OGPPoo about oGPoo ϊ] ο about OPAG i δ P g | ϊ and  1 - · | -. ^ || in | i] o | i1i | oo ΠΠοοίηο Wlooo TOIfloo t g 0 0 fi 0 0 - t d 0 0 l 0 about t e 0 0 0 1 ^{1 1} j ⁰ i η η l 7 | ΪΙ 1 1 0 0 0 L 1 2 3 4 5 and Chet 0 Odd 0 _ Odd L 1 - even p o__X Fiz. 2