RU1788592C - Device for search of pseudorandom sequence - Google Patents

Abstract

Usage: communication system with noise-like signals, Summary of the invention: a pseudo-random sequence search device comprises a low-pass filter 1, a clock generator 2, an analog-to-digital converter 3, a frequency divider 4, switches 5, 12, 17, 19, an address counter 6, OR elements 7, 26, cycle counter 8, control signal generators 9, 10, registers 11.21, SRP generator 13, AND element 14, accumulation trigger 15, arithmetic logic unit 16, detection trigger 18, random access memory 20, threshold block 22, cells Chi 24, 25, 27 shift register with feedback bonds. The device allows to reduce the search time of a pseudo-random sequence (SRP). 1 sludge, 1 tablet

Description

The invention relates to radio engineering and can be used in communication systems with noise-like signals.

Closest to the technical nature of the proposed device is a pseudorandom sequence search device. However, the prototype device has the disadvantage of a large signal search time.

An object of the invention is to reduce signal search time. .,.

The goal is achieved in that the device containing the first entrance. low-pass filter, serially connected clock generator and frequency divider, address counter and first OR element, the outputs of which are combined, cycle counter, pseudo-random sequence generator, detection trigger, sequentially switched on random-access memory block and threshold block, are added sequentially connected analog -digital converter, first switch, first register and arithmetic-logic unit, second and third switches connected in series, first and second the second control signal shapers: AND element, accumulation trigger, fourth switch, second register, the outputs of which are connected to the second inputs of the first switch and the arithmetic-logical unit, delay trigger, two keys, the second OR element and shift register with feedback while the output of the low-pass filter is connected to the first input of the analog-to-digital converter, the second input of which is connected to the first output of the frequency divider, the second input of the address counter, the input of the pseudo-random generator For the first time, and the first input of the second key, the group of second outputs of the frequency divider is connected to the group of first inputs of the second driver of control signals, the group of second inputs of which is connected to the group of first outputs of the loop counter, the third input of the first switch is connected to the third input of the third switch and to the first output of the trigger and the second output of which is connected to the second input of the loop counter, the group of the first outputs of the address counter is connected to the group of the first inputs of the second switch, the group of the second the inputs of which are connected to the group of the first outputs of the first driver of the control signals, the second output of the address counter is connected to the first input of the first driver of the control signals, the second

the input of which is connected to the output of the first OR element, and the second output to the fourth input of the fourth switch, the first input of the first OR element is connected

to the second inputs of the loop counter and trigger; accumulation, and the second input is connected to the first output of the detection trigger, the first input of the delay trigger and the first output of the device, the first input of the counter of cycles is connected to the second inputs of the element And and the trigger of the delay, and the second output of the pseudo-random sequence generator, the group of the first outputs of which is connected to second input group

5. of the third switch, the third output of the first driver of the control signals is connected to the fifth input of the fourth switch, to the second input of the first key and to the third input of the shift register with feedback, the group of first inputs of which is connected to the group of second inputs of random access memory and with the group of outputs of the third switch, the fourth output of the first driver of control signals is connected to the first input of the element And, the output of which is connected to the first input of the accumulation trigger, the group of the first, second x and the third outputs of the second driver of the control signals are connected respectively to the groups of the first, second and third inputs of the fourth switch, the group of outputs of which is connected to the second group of inputs of the first register, the second group of inputs of the second register,

5 by the third group of inputs of the arithmetic-logical unit, the third group of inputs of the operational storage unit, the group of outputs of the arithmetic-logical unit is connected to the first group of inputs of the operational storage unit, the group of outputs of which is connected to the first group of inputs of the second register, the first input of the detection trigger is connected to. the second input of the device, and the second input is connected to

5 by the first input of the second OR element and the output of the first key, the first input of which is connected to the output of the threshold block, the output of the delay trigger is connected to the second input of the second key, the output of which

0 is connected to the second input of the second OR element, the output of the second OR element is connected to the second input of the feedback shift register, the output of which is connected to the second input of the device.

5 A block diagram of the proposed device is shown in the drawing, where the following notation is adopted: 1 - low-pass filter (low-pass filter): 2 - clock pulse generator (GTI); 3 - analog-to-digital Converter (ADC); 4 - frequency divider; 5, 12. 17,

 19 - switches; 6 - address counter; 7, 26 - OR elements; 8 - cycle counter; 9, 10 - control signal conditioners (FUS); 11, 12 - registers; 13 - pseudo-random sequence generator (PSP); 14-element 15-accumulation trigger; 16 - arithmetic-logical unit (AL B); 18 is a detection trigger; 20 - operational storage unit (03B); 22 - threshold block; 23 - delay trigger; 24, 25 - keys ;; 27 is a feedback shift register (POCC).

The block diagram of the proposed device has the following functional connections: input sequentially connected low-pass filter 1, ATSPZ, switch 5, register 11, AL B16, OZB20 and register 21, the outputs of which are connected to the second inputs of ALB16 and switch 5, serially connected GTI2, frequency divider 4 , address counter 6, switch 12, the outputs of which are connected to the second inputs of the switch 17, the first inputs of the switch 17 are connected to the first inputs of the generator PSP 13, the second output of which is connected to the second input of the element And 14, the first input of the counter Iklov 8 and the second input of the delay trigger 23, the inputs of the switch 17 are connected to the second inputs. OZB20 and the first inputs of the PCOS27, the first output of the frequency divider 4 is connected to the second input of the ADC. to the input of the PSP13 generator and to the first input of the key 25, the second outputs of the frequency divider 4 are connected to the first inputs of the FUS10, the second inputs of which are connected to the first outputs of the cycle counter 8. the first, second, and third groups of outputs of the FUS10 are connected to the first, second, and third groups, respectively the inputs of the switch 19, the fourth input of which is connected to the second output of FUS9, the fifth input of the switch 19 is connected to

the third output of the FUS9., and the third input of the PCOS27 and the second input of the key 24, the first input of which is connected to the output of the threshold block 22, and the output is connected to the first input of the OR element 26 and the second input of the detection trigger 18, the inputs of the threshold block 22 are connected to the outputs of OZB20 , the group of outputs of the switch 19 is connected to the second group of inputs of the register 11, the second group of inputs of the register 21, the third group of inputs ALB16, the third group of inputs OZB20, the third input of the switch 5 is connected to the first output of the accumulation trigger 15 and the third input of the switch 17, in the second output of the accumulation trigger 15 is connected to the second input of the cycle counter 8, the second output of the cycle counter 8 is connected to the second input of the trigger

accumulation 15. to the first input of the OR element 7 and the second input of the address counter 6, the second output of which is connected to the first input of the FUS9, the output of the detection trigger 18 is the first output of the device, connected to the first input of the delay trigger 23 and connected through the second input of the OR element 7 to the second input of FUS9, the first outputs of which are connected

0 with the second inputs of the switch 12, and the fourth output is connected to the first input of the And 14 element, the output of the And 14 element is connected to the first input of the accumulation trigger 15, the first input of the detection trigger 18

5 is connected to the second input of the device, the output of the delay trigger 23 is connected to the second input of the key 25, the output of which through the second input of the OR element 26 is connected to the second input of the PCOS27, the output of the PCOS27 is the second output of the device.

The proposed device operates as follows.

With the arrival of an external pulse Setting on the S input of the detection trigger 18

5, the device is put into the memory bandwidth search mode, which consists of steps; 1) accumulation; 2) fast Walsh correlation transform (BKPU); 3) reading. With this signal, the detection trigger 18 is set to the log state by the inverse output. A. Signal log. 0m from the inverse output of trigger 18 through the OR element 7 is fed to the R input of the FUS 9 and removes its zero initial setting -. After removing the zero

5 of the initial installation of the FUS9 under the action of the counting end pulses (IOS) received from the transfer output of the address counter 6 generates an accumulation start pulse (TIN). IOS address counter

0 6 are clock for FUS9 and follow continuously, since the address counter 6 constantly works in the counting mode of clock pulses coming from the GTI2 through the frequency divider 4.

5 INNSFUSE enters through the element And 14, where it is linked to the pulse of the end of the sequence (ICP) of the PSP13 generator, to the S input of accumulation trigger 15 and transfers it directly

0 exit to the log state. 1, and by inverse: exit to the state log. A. The signal from the direct output of the accumulation trigger 15 is the first control signal to the switches 5, 17 (CMS1). QMS level 1 log.

5 1 switches the switches 5, 17 in such a way that signals of the accumulation stage begin to pass to their outputs. Similarly, under the action of the CMS2, CMS level log O received from the FUS9, the switch 19 begins to pass output signals from the FUS10 of the accumulation stage. CPS is also fed to the control input of key 4 and the log level. He keeps him closed. In addition, the signal log.0 from the inertial output of the accumulation trigger 15 reaches the R input of the accumulation cycle counter 8 and removes the zero initial setting. From this moment, the cycle counter starts reading the ICP of the GENERATOR

psptz ..

The output SRP at the accumulation stage, the filtering field in the low-pass filter 1 is fed to the ATSP, where, using clock pulses from the frequency divide 4, sampling is performed, its time and level quantization. Converted in ADC to the digital form of the memory bandwidth by a parallel n-bit code, through an open switch 5, it enters the input of the register 11, in which it is recorded using the first clock pulses of the register (TIR d.1) with the information repetition rate. In the first cycle of the accumulation step (recording the first length of the SRP), the signal from the output of the register 11 is fed directly to the OZB20 through ALB16. The direct information transmission mode is provided in ALB16 using control signals: M - operation mode, (S.1 ... S4) .- choice of function (VF), Cn - transfer coming from switch 19. The output signal of information is recorded in OZB20 at the rate of its arrival at the addresses (A0 ... Am) supplied from the PSP generator 13 through the switch 17, under the action of control signals: K-chip, s / s — write / read, coming from the output of the switch 19. Generator PSP13 is made according to the scheme with built-in adders, therefore, when recording the signal of the input PSP in OZP20 at of the generator 13 itself, permutations of the SRP elements are carried out and, thereby, the SRP is transferred to the basis of the Walsh functions. Thus, at the end of the first cycle, at the end of the first cycle, in OZB20 there is a recorded first SRP in the form of one of the implementations of Walsh functions. The end of the first accumulation cycle is fixed by the cycle counter 8 by recording the first ICP in it from the PSP13 generator. As the counter, FUS10 determines the end of the first cycle of the accumulation step and changes the control signals of the WF S2 and M for ALB16 from the log level. 1 to level log. Oh, and the WF S1 signals are from the log level. About rfa level log. A. Under the influence of altered control signals of the WF Si. 82 and M, ALB16 is put into the summation mode of the input signals. The beginning of the second cycle at the stage of accumulation of information of the previous cycle is written out using control signals s / s and VK from OZB20

to the addresses of the PSP 13 generator, it is rewritten under the action of TIR2, coming from the switch 19 to the 21 m register, it is summed up with the information coming back to ALB16. The result of the sum at the end of each clock interval is recorded again in the OZB20 cells at the addresses of the PSL13 generator. This happens until the counter 8 cycles counts

0 number of accumulations.

As soon as the last ICP is written to the cycle counter 8 from the SRP generator 13, the accumulation end pulse (ION) appears at the output of the cycle counter 8 transfer, which is fed to the R inputs of the address counter b and the accumulation trigger 15 and, through the OR element 7, to R input FUS 9. The ION is reset to address counter 6, FUS9 and accumulation trigger 15 to the initial state.

0 Thereby, a circuit of logical levels of control signals of the switches is made for switching them to the BCU.PU stage and the preparation of the address counter 6 and FUS9 for operation at the BCU stage from the initial state5. Signal level log. 1, from the inverse output of accumulation 15, it is supplied to the R input of the cycle counter 8 and resets it to the zero state, which is held until the beginning. the next stage. accumulation (regular

0 state change of accumulation trigger 15). QMS1 from the direct output of the accumulation trigger 15 level log. О switches the switch 5 in such a way that a signal from the output of the register 21 begins to pass through it, and the switch 17 switches to the transmission mode of the signal from the switch 12. In addition, under the action of the QMS level 2. 1 and CPS level log. About the switch 19 switches to the output the control signals of the BKPU mode coming from the FUS10. At the BKPU stage, the SRP implementation recorded in OZB20 is multiplied by the Hadamard matrix, i.e. calculation of correlation coefficients with functions

5 Walsh. For this, at the BKPU stage, the addresses (A0 ... Am) on the OZB20 are received from the address counter b through the series-connected switches 12; 17. The BKPU stage itself is divided into several cycles, the duration

0 of which is determined by the period of operation of the address counter 6, and the cycle number is determined by the state of FUS9. Depending on the cycle number BKPU, set FUS9, using the switch 12 is a permutation of

5 cycles to a cycle of output bits of addresses of the address counter 6 according to a certain algorithm, in accordance with a known graph.

The process of calculating the correlation coefficients with Walsh functions is carried out as follows. At the BKPU stage, in the first cycle under the influence of control address signals (A0 ... At). The pairs of numbers (0 and 1, 2, 3, 4 and 5, etc.) standing next to each other are written to C and s / s from OZB20 and then stored in register 11 and register 21, respectively. Using WF control signals , Sp, M in AL B16, the addition and subtraction of 11.21 pairs of numbers in the registers is performed sequentially. The resulting sums and differences are recorded in the memory cells of the OZB20, and are recorded in the cell from which the first term was read, and the difference is written in the cell from which the second term was read, i.e. butterfly operation is performed. With the end of the first BCCH cycle, the address counter b generates an IOS, which is recorded in the FSL9 and indicates the beginning of the second cycle. In the second cycle, FUS9 forms the QMS (4 ... Q) according to the second cycle of the control panel, under the influence of which the switch 12 changes the order of address sequence (A0 ... At) from the address counter 6 and sets them in accordance with the second cycle of the Wadsh graph -Adamara. During this cycle, the numbers Oi2, 1 and 3, 4 and 6, etc., are also written in pairs at the rearranged addresses (Do ... Am), and then the same butterfly operation is performed with them as in the first cycle. Subsequently, the operation of the device at the BCCH stage occurs similarly to the two cycles described above, and the addresses (A0 ... Am) for OZB20 are rearranged from cycle to cycle in accordance with the graph. Thus, by the end of the BKPU stage in OZB20, the correlation coefficients of the received SRP with the Walsh functions are recorded.

As soon as the FUS9 reads the specified number of BCPU cycles from the address counter 6 according to the IOS from the address counter 6, the SEC level log is formed at its outputs. 1 and QMS level 2 log. Oh, with the advent of which the device proceeds to the reading step. Under the action of the CMS and CMS2 of these levels, the switch 19 switches the control signals of the read stage to the output from the FUS10. Besides. CPS level log. 1 closes the key 24 and switches the PCOS27 in the mode of parallel recording of the signal. FUS9 also forms at the stage of reading the QMS (4 ... O) of a type in which addresses (Ao ... Am) from the address counter 6 pass through the switch 12 in the normal order (not rearranged). Using the control signals of the read stage, the OZB20 switches to the read mode. Read from OZB20 information is supplied to the threshold block 22. If the threshold is exceeded, then the output

threshold unit 22 is an information detection pulse (IOI). This pulse through a closed key 24 is fed to the R-input of the detection trigger 18 and sets it to the log state on the inverse output. 1, Log level signal, 1 from the inverse output of the detection trigger 18 and is the output of the device information detection (SDI). In addition, the IOI from the output of the key 24 is fed through the OR element 26 to the PCOS27 synchronization input and writes the address number (A0 ... Am) from the switch 17 of the OZB20 cell in which the information was detected, in parallel to PCOS27, i.e. the correlation coefficient exceeded the threshold value. SDI from the inverse output of the detection trigger 18 passes through the OR element 7 and stops the operation of the FSF9, resetting it at the input R to the zero state. Formed through this CPS level log. About with FUS9 opens the key 24 and switches PCOS27 in sequential recording mode. SDI from the inverse output of the detection trigger 18 also goes to the information input of the delay trigger 23, the synchronization output of which is supplied by the ICP from the SRP generator 13. Here, the SDI is connected to the clock ICP, i.e. The SDI at the output of the delay trigger 23 appears with some delay due to the time of the appearance of the first ICP from the moment the SDI arrives at the input. SDI from the output of the delay trigger 23 enters the control input of the key 25 and puts it in a closed state. Clock pulses from the output of the frequency divider 4 through the closed key 25 and through the OR element 26 are fed to the synchronization input РСОС27, and, under the influence of these pulses, РСОС27 starts generating the SRP from the initial state, caused by the written parallel address code of the OZB20 cell in which it was detected information, i.e. synchronously with the received memory bandwidth. The output signal from PCOS27 is the second output signal of the device.

If the threshold in the threshold block 22 is not exceeded when reading information from OZB20, then at the end of one reading cycle FUS9 under the action of IOS from the address counter 6 generates a TIN, under which the entire process of searching for a signal is automatically repeated again until the signal detected.

The technical efficiency of the proposed device in comparison with the prototype device can be shown in the following example. Maximum SRP Search Time

in the prototype device is defined by the expression: ...

M-N tggp

1h TT

TnakI M K-L

where Tna.kg

M-L

- the duration of the accumulated segment of the input signal;

M is the conversion factor of the cycles of the 19 prototype;

L is the number of bits of registers of 4 types for one sample on the length

PSP; ...; ..,. , .... N is the number of elements of the SRP;

fs,.; - -..-. ::. :

to

TS

Ss is the clock frequency of the register 5 protO type; .. / -. ,. ..;. ...:. . .;.

Sm-clock frequency of the input memory bandwidth. .-. The maximum search time SRP in the proposed device:

.2 + about I092N,

X-N

ITTV.

signal accumulation time where Tnak. 2

 la; . . v ...: -.,. -:, -. . . ... ,, -...- y - the number of accumulated periods

PSP; ,. /; ./;.; . ... ...-. . ,,:

Those - the time of performing one butterfly operation (reading two numbers from the OZB, summing, calculating and writing the results in the OZB)

With the same noise immunity of devices (Tnak. 2), the time taken to search for a prototype device is more than the number of times equal to:

Tv

T2

N

N

Tb

K -1/1. ) with. I nak.

N-l

 L (f5-fm) (1+ n-log2N)

 -.

Based on the speed of the existing element base, we can put it. In order to determine practically feasible L values, it is necessary to evaluate the dependence of the volume of the apparatus of the prototype device on the length of the registers 4, 5 of the prototype. When using prototype microcircuits of type 533IRT6 (4-bit registers) for building blocks 4.5 of the prototype, and 533LP5 (four modulo adders for building block b of the prototype)

two) and 533IPZ (4-bit AL B) the total number of buildings in blocks 4, 5, 6, will be:

 - | L,,.

and their power consumption

  Rir + Rlp + Rip) ;; ..

where Rir is the power consumption of the chip 543IR16 (115mW);

RLP is the power consumption of the 533LP5 microcircuit (50 mW);

Rip is the power consumption of the 533 IPZ microcircuit (184, 25 mW). The table shows the values of NK and P for some L.

 Based on the table, it can be seen that the practical implementation of the prototype device is advisable with L not more than 64.

, -., ..,. ,,,:: ,,: ..: .. -:,.; -. -.

Formula from acquisition A pseudo-random sequence search device containing a low-pass filter, the input of which is the first input of the device, a clock generator and a frequency divider, as well as a pseudo-random sequence generator (PSP), a cycle counter, a detection trigger, an address counter, an input a reset of which is connected to the first input of the first OR element, and serially connected random access memory and a threshold block, characterized in that

that, in order to reduce the search time of the memory bandwidth, it is connected to it with a series-connected analog-to-digital converter (A1DP), a first switch, a first register and an arithmetic-logic unit, series-connected second and third switches and a shift register with feedback, the first and second control signal drivers, AND element, accumulation trigger, fourth

a switch, a second register, the outputs of which are connected to the corresponding group of inputs of the first switch and the arithmetic logic unit, a delay trigger, keys, and a second OR element, while the output

0 low-pass filter is connected to the ADC input, the clock input of which is connected to the first output of the frequency divider, with the input of the address counter, the input of the PSP generator and the input of the first key, the other outputs of the frequency divider are connected to the first group of inputs of the second driver of the control signals, the second the group of inputs of which is connected to the corresponding outputs of the cycle counter, the control input of the first switch is connected to the control input of the third switch and to the direct output of the accumulation trigger, whose inverse output is connected to the installation input of the loop counter, the outputs of the address counter are connected to the corresponding input of the second switch, the control inputs of which are connected to the corresponding outputs of the first driver of control signals, the clock input of which is connected to the transfer output of the address counter, and the installation input of the first driver of control signals is connected with the output of the first OR element, the first input of which is connected to the corresponding output of the cycle counter and the first input of the accumulation trigger, and the second the first input of the first OR element is connected to the inverse output of the detection trigger and the first input of the delay trigger, the counting input of the cycle counter is connected to the first input of the AND element, the second input of the delay trigger and the first output of the SRP generator, the other outputs of which are connected to the corresponding inputs of the third switch, the output of the first the control signal of the first driver of control pulses is connected to the first control input of the fourth switch, and the output of the second control signal is connected to the second control input of the fourth of the switch control input of the second switch and a control input of a shift register with feedback bonds, which group of inputs coupled to respective address inputs

operational memory unit, the output pulse of the beginning of accumulation of the first driver of control pulses through the element And is connected to the second input of the trigger trigger, the first, second and third

groups of outputs of the control signal of the second driver of control signals through the fourth switch are connected to the control inputs of the first and second registers, random access memory

block and arithmetic-logical block, the outputs of which are connected via random access memory to the corresponding inputs of the second register, the output of the threshold block through the second

the key is connected to the first input of the detection trigger and the first input of the second OR element, the second input of which is connected to the output of the delay trigger through the first key, the output of the second OR element is connected to the corresponding input of the shift register with feedback, the second input, the inverse output of the detection trigger and the feedback register shift output is respectively an input

pulse installation, the first and second outputs of the device.