SU771891A2 - Discrete matched filter - Google Patents

Description

one

The invention relates to the field of radio engineering and can be used to synchronize radio communication systems.

According to the main author. St. 1 522547. 5 is known a discrete matched filter comprising a clock pulse generator, a shift register, an adder, a pseudo-random sequence generator, a polynomial 10 delay register, a decoder, a switch and a series-connected shaper pulse generator and an OR element, the output of which is connected to the clock inputs of the shift register, bit outputs The codes of which are connected to the corresponding inputs of the switch, the output of which is connected to the information input of the shift register and to the adder, the second input of which is connected with the generator of pseudorandom sequences, the output of the clock generator is connected to another input of the OR element and to the pulse shaper generator, the output of which 25 is connected to the clock inputs of the pseudo-random sequence generator, the installation inputs of which are connected to the register of the delay polynomial and the decoder, connected 30

to the input of the switch and the installation input of the pulse shaper.

However, when different sequences are selected in a known discrete matched filter, their mutual temporal arrangement is not fixed, which does not allow to separate composite sequences and fragments of signals with time-coded sequences among themselves.

The aim of the invention is to provide the possibility of separating composite recurrent pseudo-random sequences.

For this, a discrete matched filter containing a textual pulse generator, a shift register, an adder, a pseudo-random sequence generator, a delay polynomial register, a decoder, a switch, and a series-connected shaper of a pulse train and an OR element whose output is connected to the clock inputs of the shift register, bit outputs which is connected to the corresponding inputs of the switch, the output of which is connected to the information input of the shift register and to the adder, the second input of which is n with a pseudo-random sequence generator, while the output of the clock pulse generator is connected to another input of the OR element and to the pulse shaper driver, the output of which is connected to the clock inputs of the pseudorandom sequence generator, the setup inputs of which are connected to the register of the delay polynomial and the decoder connected to the switch input, and to the setup input of the pulse builder, a sequentially connected trigger, a valve, a first counter and a coincidence unit, as well as e the inverter and the second counter connected in series, the second input of which is connected to the output of the adder, the first trigger input and the second input of the coincidence unit, the output of which is connected to the input of the inverter and the second input of the first counter, and the output of the clock generator is connected to the second input of the valve, and the corresponding register of the delay polynomial is connected to the third input of the coincidence block, and the output of the second counter is connected to the second trigger input.

The drawing shows a structural electrical circuit of a discrete matched filter.

The filter contains 1 clock pulse generator, shift register 2, adder 3, pseudo-random sequence generator 4 (PSP), delay polynomial register 5, decoder b, switch 7, driver pack 8, element 9, trigger 10, valve 11, first counter 12 times, block 13 matches, inverter 14, second counter 15 fragments.

The filter works in three stages, representing, respectively, writing the input sequence symbol to shift register 2, comparing the current code state of shift register 2 with the generator 4 reference sequence, fixing the relative time to obtain a convolution of the composite composite random sequence (CSP)

At the first stage, X1, each clock pulse of generator 1 writes a binary symbol (1 or O) of the input sequence to shift register 2 and shifts the memory bandwidth while register feedback 2 is off.

The second stage begins with the start of the imaging unit 8, the output pulses of which through the element OR 9 arrive at the clock inputs of the shift register 2 and the generator 4 and synchronously start them. In this case, the shift register 2 works in a ring mode, and the number of pulses in a burst (N) is equal to the number of characters in the reference sequence and the number of bits in shift register 2. The frequency of the pulses in the burst must be greater than N - f, j, where fi is the pulse frequency of the generator 1.

As a result, at the output of the shift register 2 through the switch 7, a sequence of pulses will be recorded in the shift register 2, i.e. the input, and at the output of the generator 4, the reference sequence.

The intermediate (current) comparison stage ends with the next clock pulse, which records the next character and restarts the 8 bursts of pulse generator. Thus, over a period of one clock

The 5th pulse records the next character and compares the recorded input sequence with the reference bandwidth.

The number of matching signals

0 calculates adder 3 and, with the required number of the latter, a sync of synchronization (convolution) is formed at its output.

5 Upon receipt of the convolution signal, the memory bandwidth at the output of the adder 3 at the third stage of the filter operation, the trigger 10 is set to one, thereby opening the valve 11 to pass the reference pulses from the generator 1 to the input of the time counter 12. At the time of the arrival of the next (next) signal from the output of the adder 3 on the block 13 coincidence is made

comparison of the code states of the bits of the counter 12 and the time shift between the memory bandwidth recorded in register 5. If there are coincidence of time shifts, the output signal from the coincidence block 13 sets to the initial state

0, the time counter 12, a. In the absence of a match, the inverter 14 generates a reset signal for the fragment counter 15, which counts the number of elements of the composite memory bandwidth and, when the required amount is reached, enters the signal at the output of the device. In this case, the signal from the output of the counter 15 fragments sets the trigger 10 to the zero (initial) state before the next duty cycle.

The structure of the code and the length of the reference sequence are specified by the minute delay. The temporal characteristics of composite memory bandwidths are determined by the relative time interval between memory band fragments, whose values are encoded in binary numbers and stored, as well as the delay polynomial, in register 5 of the delay polynomial.

Invention Formula

Discrete matched filter auth. St. 522547, characterized in that, in order to enable the separation of composite

recurrent pseudo-random sequences, a sequentially connected trigger, a gate, a first counter and a match block, as well as a successively connected inverter and a second counter, the second input of which is connected to the output of the binder, the first trigger input and the second input of the match block, the output of which is connected to the input of the inverter and the second input of the first counter, the output of the clock generator is connected to the second input of the valve, and the corresponding output of the register of the delay polynomial is connected to There is a matching input for the coincidence unit, with the output of the second counter connected to the second input of the trigger.

Claims (1)

60 claims Discrete matched filter by ed. St. No. 522547, characterized in that, in order to ensure the possibility of isolating composite recurrent pseudorandom sequences, a serially connected trigger, a gate, a first counter and a matching block are introduced, as well as a serially connected inverter and a second counter, the second input of which is connected to the output of the adder, the first trigger input and the second input of the coincidence unit, the output of which is connected to the inverter input and the second input of the first counter, while the output of the clock generator is connected to the second input valve house and the corresponding output of register lot - the delay member ³ is connected to a third input of block matching, the output of the second counter is connected to the second input flip-flop.