SU915269A1 - Device for synchronizing m-sequence with inverse modulation - Google Patents

Description

The invention relates to radio engineering and can be used to synchronize and search for a pseudo-random pt sequence with inverse modulation. <

A device ^is known ^- synchronization of a go-sequence with inverse modulation, containing serially connected information converter ~ ₁₀ mation and correlator, to another input. which is connected to the output m-sequence generator, a first counter connected in series and the first decoder and sequentially soe- union of the second counter ₁₅ and the second decoder, and deciding unit [1].

However, the known device does not have a sufficiently high noise immunity and a relatively long synchronization time.

The purpose of the invention is to increase the noise immunity and reduce the time of entry into synchronism,

2

. The goal is achieved by the fact that the AND and OR elements are entered into the t-sequence synchronization device with inverse modulation and the key block while the output of the correlator is connected to the input of the decision block, to which the 1st outputs through the key block and the k-th output directly connected to the inputs of the first element OR, whose output through the second element OR is connected to the control input of the decision block and directly to the installation inputs of the t-sequence generator, the first and second counters, k-1-5 outputs of the first decoder connected to other inputs of the key unit and through the third element ORI to one of the inputs of the AND element, to the other input of which the first output of the second decoder is connected, and the output of the AND element is connected to the corresponding input of the first counter via the fourth element OR, to the other input of which is connected second exit

3 915269 4

the second decoder, the third output of which is connected to the corresponding input of the w-sequence generator, to the signal input of which the output of the information converter is connected, * and the clock input is combined with the corresponding input of the second counter, with the kth output of the first decoder element OR. 1C

The drawing shows a structural electrical circuit of the proposed device.

The synchronization device of the w-sequence with inverse modulation and 'contains an information converter 1, a correlator 2, a decisive block 3 "a block 4 of keys, containing a K-1 of And 5-7 ^ elements, an 8-t generator, containing And 9, trigger 10, 2 (

the switch 11 and the generator 12, the first and second counters 13 and 14, the first and second decoders 15 and 16, the element And 17 and the four elements OR 18-21.

The device works as follows 22

in a way.

The received video signal of the ω-sequence is fed to the input of the converter 1. At the output of the generator 8, in the presence of synchronization, a synchronous and in-phase t-sequence with the received signal is formed. The synchronization state is marked by the generation of a signal of a unit level at the output of the third ₃ , the element OR 20, which is connected to the first input of the element AND 17.

At one of the inputs of the generator 8 and the second counter 14 are continuously clock pulses to synchronize the operation of the entire device "

The device works in the modes of recording, checking th synchronization "

I ·

8 the initial state of the trigger 10, the counters 13 and 14 and the outputs of the decisive * '· unit 3 are reset. Recording mode used for recording into register 12, the generator initial segment symbols m-sequence, which begins with the formation of con- ³¹ tinuous sequence and its search method of the stepper correlator "

The signal from the third output of the second decoder 16 through the element And · 9 trigger 10 is set to one state, which ensures the passage of a segment of characters from the inverter 1 through the switch 11

in the register of the generator 12. Converter 1 thus removes the inverse modulation from the characters of the input t-sequence. After a set time sufficient to fill the entire register of the generator 12, the trigger 10 switches to the zero state, in which the generator 12 closes through the second input of the switch.

From this moment begins the test mode, which has a k-1 stage. In test mode, the first counter 13 signals from its outputs determines the stage number of a multi-stage decision-making procedure. In the ϊth stage, a signal appears at the 1st output of the first decoder 15. The correlator 2 and decisive block 3 in the test mode form the value of the mutual correlation function by counting the number of symbol mismatches at the inputs of the correlator 2. If the recorded segment of characters in the generator 12 did not contain errors and during the duration of the first stage the number of discrepancies is less than the first threshold, then the device moves to the second stage of the test.

Similarly, if the total number of inconsistencies in the previous 2 ^{stages is} less than the threshold of this stage, then the device goes into 1 + 1 stage, ·

When it comes to the th stage, the device goes into synchronization mode. The duration of the respective stages is determined by) the first decoder 15 and the period of the signals at the second output of the second decoder 16.

If at any ίth stage of the check the number of discrepancies generated by the correlator 2 and the decision block 3> is greater than the threshold, then on the GM output of the decision block 3 a single signal arises, which through the elements OR 18 and 19 returns to the zero state the decision block 3 »Trigger 10 and the first and second counters 13 and 14. The device enters the recording mode. After all the K-1 stages have expired, the device goes into synchronization mode, in which the output sequence of reference symbols — from generator 12 — is in-phase and synchronous with the received symbols arriving at the input of converter 1. The presence of synchronization mode is indicated by the generation of a signal at the output of the element OR 20, B synchronization mode decisive block 3 continuously for

5 915269 6

analysis time carries out a verification of the total number of inconsistencies per stage with a threshold.

After the analysis time at the km output of the first decoder 15 5

a pulsed signal appears, dropping through the OR 19 element to zero the number of mismatches accumulated by the decision block 3.

If a synchronization ’of synchronism occurs in the synchronization mode, then is it the kth exit? the decision block 3, a signal appears that returns the device through the first element OR 18 to the recording mode. 15

The presence of such a multi-step procedure increases the noise immunity of the device and reduces the time of entry into synchronism.

20

Claims (1)

Claim An inverse modulated t-sequence synchronization device containing a serially connected 5 information transformer and a correlator, to another input of which the output of the t-sequence generator is connected, the first counter and the first counter of the encoder and the second counter and second decoder and decider, characterized in that, in order to improve noise immunity and $ ₃ the reduction scheniya occurrence in time synchronism, elements AND and OR and a key block are entered, while the output to the correlator is connected to the input of the decision block ^ k-1-th outputs of which through the key block and the k-th output are directly connected to the inputs of the first OR element, the output of which through the second OR element is connected to to the control input of the decision block and directly to the installation inputs of the t-sequence generator, the first and second counters, the k-1st outputs of the first decoder are connected to other inputs of the key block and through the third OR element to one of the inputs of the AND element, to another input at which the first output of the second decoder is connected, and the output of the AND plug to the corresponding input of the first counter through the fourth OR element, to the other input of which the second output of the second decoder is connected, the third output of which is connected to the corresponding input of the t-sequence generator, to the signal input of which is connected the output of the information converter, and the clock input is combined with the corresponding input of the second counter, the kth output of the first decoder is connected to another input of the second element I I.