SU1312750A2 - Device for locking in step with m-sequence - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to improve synchronization accuracy by reducing synchronization failures. The device contains a low-pass filter 1, a multiplier 2, switches 3, 13 and 20, synchronization detection detector 4, control unit 5, receive unit 6, shift registers 7, 15 and 18, coincidence adder 8, threshold block 9, g - p 10 clock frequency, divisors II and 17 frequencies, adder 12, rr. 14 pseudo-random sequence, trigger 16, majority element 19, key 21, selector of 22 fronts, counters 23 and 25 and driver 24 control pulses. In this device, the velocities of the following characters of the pseudo-random sequence of the input signal and the signal of local g-14 are equalized, which leads to a decrease in the probability of failures. The goal is achieved by the introduction of the switch 20, the key 21, the selector 22, the counters 23 and 25, and the driver 24. 1 Il. sl 1h

Description

The invention relates to radio engineering, can be used in communication systems with noise-like phase-manipulated signals, and is an improvement of the device according to the main author. No. 1003371,

The purpose of the invention is to improve synchronization accuracy by reducing synchronization failures.

The drawing shows an electrical block diagram of a synchronization device with an M-sequence.

The synchronization device with the M-sequence contains a low-pass filter 1, a multiplier 2, a first switch 3, a synchronism detection detector 4, a control unit 5, a receive unit 6, a first shift register 7, a coincidence adder 8, a threshold unit 9, a generator 10 clock frequency, first frequency divider II, adder 12, second switch 13, pseudo-random sequence generator 14, second shift register 15, trigger 16, second frequency divider 17, third shift register 18, majority element 19, third switch The phone 20, the key 21, the separator 22, the first counter 23, the driver 24, the second counter 25.

The device works as follows.

The signal of the received pseudo-random binary sequence is filtered in low-pass filter 1 and fed to multiplier 2 and block 6 by element-by-element reception, in which as they arrive, the memory bandwidth is evaluated and written to the first shift register 7. The second shift register 15 receives the symbols of the local sequence, generated by the SRP generator 14. In the signal search mode, the frequency of the reference bandwidth is (k + 1) times the frequency of the received bandwidth. As a result, at each shift of the samples of the first shift register 7 there is a (k + l) shift in the second shift register 15. At each step of the sample shift, located in the second shift register 15, a bitwise comparison of information stored in the first and second shift registers 7 and 15 is made, and the sum of the number of matching bits is calculated.

five

0

five

0

five

0

five

0

five

doses, which is compared with the threshold in threshold block 9,

When the threshold at the outputs of the threshold block 9 is exceeded, the voltages corresponding to the logical units that receive the information input of the third shift register 18 and one of the inputs of the trigger 16 are set, set it to a new state. The output signal of the trigger 16 permits the recording of information in the third shift register 18 and the operation of the second frequency divider 17. The latter produces clock pulses of the third register 18 shift with a period equal to the period of the SRP, generated by the generator 14 SRP. Due to this, in the third shift register 18, the signal detection information in the threshold block 9 is recorded for the same time shift values of the input and reference signals.

This information from the output of the bits of the third shift register 18 goes to the n inputs of the majority element 19, which forms a logical unit if there are at least m from its outputs of the logical unit. If, for n clock pulses of the third shift register 18, a signal is detected less than m times, the first logical unit, recorded in the third shift register, arriving at its output, flushes the trigger 16, which sets the third shift register 18 and the second frequency divider 17 to the original condition.

If the signal is detected m or more i times, then the logical unit appearing at the output of the majority element 19 enters n, and the control unit 5. The control unit 5 skips the switches 3 and 13, as a result of which the SRP generator 14 begins to form a sequence of the same frequency as that received. In multiplier 2, the input signal is demodulated and through the open switch 3 enters the synchronism detection detector 4, in which integration is performed for each sufficiently large time interval T and the result is compared with the threshold. Exceeding the threshold confirms the presence of synchronization sequence. If the signal is below the threshold, control unit 5 sets switches 3 and 13 to their former position and the search is resumed. The clock frequency of the PSP generator 1A, in the signal search mode, is (k + l) -f, where f is the frequency of the input signal, is formed in the adder 12 by adding the signal of the clock generator 10 and the input signal of the frequency f of the first frequency divider 11. The second frequency divider 17 performs a division of the frequency k-f, equal to the relative slip frequency of the input and reference sequences, by the number N equal to the number of elements of the transmitted sequence.

The phase-shift keyed signal from the output of low-pass filter 1 is fed to the input of a front 22 selector, in which at the time the high-frequency oscillation phase is flipped, pulses are generated that are fed to the input of the first counter 23, and during the pulse, the pulse is given, which is given to the first input of the second counter 25, having set it to its initial state. The period of the full-cycle of operation of the first counter 23 is chosen equal to the duration E of the periods of the received SRP and sets the time interval through which the frequency adjustment is made. The value (selected depending on the stability of the used frequency generators in the transmitter and the receiver, as well as on the length of the SRP.

At the end of the cycle of operation of the first counter 23, a pulse is formed at its first output, during which the generator 24 of the control pulses compares the number accumulated in the second counter 25 with the nominal value stored in the controller 24 of the control pulses. In the time interval between the output pulses of the first counter 23, the third switch 20 and the key 21 are in the working position: the third switch 20 connects the output of the first divider II to the first input of the summation. Order 1980/56 Circulation 639 Subscription Outgoing-Poly. pr-tie, Uzhgorod, st. Project, 4

mat 12, and the key 21 connects the output of the clock generator to the second input of the adder 12.

If, as a result of the comparison, the number accumulated in the second counter 25 is greater than the nominal one, which indicates that the local clock frequency exceeds the clock frequency of the received signal, then the pulse from the second output of the driver 24 turns off the key 21, prohibiting the passage of one clock pulse to the second input of the adder . 12. Otherwise, a pulse appears at the first output of the control pulse generator 24, which flips the third switch 20, ensuring the passage of an additional clock pulse to the first input of the adder 12.

Thus, the device aligns the speeds of following the PSP symbols of the input signal and the local generator signal, which leads to a decrease in the probability of failures.

Claims (1)

Invention Formula The device synchronization with M-last post on avt.sv. No. 1003371, characterized in that, in order to improve synchronization accuracy by reducing synchronization failures, a third switch is inserted between the first input of the adder and the output of the first frequency depot, and the output of the clock generator is connected to the second input of the third switch, through the entered key - to the second input the adder and through the second counter and the control pulse shaper entered by it connected in series, the second output of which is connected to the third input of the third switch is connected to the second Valid key, wherein the low pass filter output connected in series through the input extractor fronts and the first counter is connected respectively to the second input of the control pulses and a second counter.