SU1042199A1 - Pseudorandom sequence search device - Google Patents

Abstract

THE SEARCH DEVELOPMENT OF A FAILED. LAST VATEL NODES CONTAINING ON INPUT a serially connected low-pass filter, a multiplier and a synchro-validation unit, serially connected power unit reception, the first shift register and the match adder g to the other inputs of which are connected. the outputs of the second shift register, serially connected clock generator and frequency divider, the output of which is connected to the first input of the switch and to the first input of the block, element-by-element reception, to the second input of which is connected the output of the low-pass filter and pseudo-random sequence generator (RSP), input which is connected to the first input of the second shift register and the second input of the multiplier, and the threshold unit, it is necessary to have, in order to increase the noise immunity of the Search, introduced follower | but connected address counter, cycle counter, detection trigger, one-shot and additional frequency divider, valve block connected in series, arithmetic adder and real-time storage block, and OR element whose output is connected to the second input of the switch, the third input combined with the input one-shot, and the output is connected to the second input of the second shift register and the second input of the additional frequency divider, the output of which is connected to the input of the SRP generator, while complementing A clock pulse generator output is connected to the corresponding input of the random access memory unit, to the Additional inputs of which the corresponding outputs of the address counter are connected, the first input of which is combined with the second input of the cycle counter and the second input of the trigger detection unit and connected to the output of the synchronization confirmation block , the second input of which is connected to the output of the detection trigger, the third input of which is connected to the output of po4; horn block, whose input is connected to the outputs of the operational storage unit and the input of the valve unit, to another input of which is connected; the second output of the cycle counter is connected, the output of the clock generator is connected to the second input of the address counter and the first input of the control element OR , the second input of which is connected to the output of the frequency divider.

Description

The invention relates to radio engineering and can be used in communication systems with noise-like and phase-shifted signals. A device for synchronization of noise-like signals is known. It contains two multipliers each of the inputs, the other inputs of which are connected to the corresponding outputs of the reference voltage generator, as well as an adder, two integrators, two converters, digital-analog, two analogue converters, a modulator of signals , switch, threshold block, two shift registers, N drives, N + 2 additional adders, with the output of each multiplier through the series-connected corresponding integrator, The analogue pattern maker, the shift register and one of the additional sugators, to the other input of which the input of the shift register is connected, are connected to one of the inputs of the signal modulators, the outputs of which through the other N additional adders are connected to another input of the corresponding additional adders and to the corresponding inputs of the switch, each output of which is connected through a digital-analog converter to the input of the corresponding quadrator, in addition, the output of the adder is connected to the input of the threshold block LI. . This device has a high noise immunity, but a relatively long signal search time. The closest to the invention is a Vi-sequence synchronization device, comprising successively connected low-pass filter, multiplier, synchronization confirmation block, pseudo-random sequence generator (PSP) switch, first shift register, sum of coincidences, and a threshold block whose output connected to the second input of the synchronization confirmation block, serially connected clock frequency generator and frequency divider, the output of which is connected to the second input of the switch to t The input input of which is connected to the output of the clock generator, while the output of the frequency divider is connected through the serial element-receiving unit and the second shift register is connected to other inputs of the coincidence adder, and the output of the SRP generator is connected to the second input of the multiplier 2. This 11-sequence synchronization device has a short search time, but its noise immunity is relatively low. The purpose of the invention is to improve the noise immunity of the search. To achieve the goal, a pseudo-random sequence finder containing a serially connected low-pass filter, a multiplier and a synchronization acknowledgment unit, a serially connected receive unit, a first shift register and a match adder, the other outputs of which are connected to the second shift register, are connected in series to the input. clock pulses and a frequency divider, the output of which is connected to the first input of the switch and to the first input of the block is element-wise of the second reception, to the second input of which the output of the low-pass filter is connected, as well as the SRP generator, the output of which is connected to the first input of the second shift register and the second input of the multiplier, and the threshold unit, are connected in series to the address counter, cycle counter, detection trigger, single-oscillator and an additional frequency divider, a valve block connected in series, an arithmetic adder and an operational storage block, as well as an OR element, the output of which is connected to the second input of the switch, the third input of which is combined with the one-shot input, and the output is connected to the second input of the second shift register and the second input of the additional frequency divider, the output of which is connected to the input of the PSP generator, while the additional output of the clock generator is connected to the corresponding input of the operational memory of the dego block; The inputs of which are connected to the corresponding outputs of the address counter, the first input of which is combined with the second input of the cycle counter and the second input of the trigger nor, and connected to the output of the synchronization confirmation block, the second input of which is connected to the output of the detection trigger, the third input of which is connected to the output of the threshold block, the input of which is combined with the outputs of the operative memory block and the input of the valve block, to another input of which the second output of the cycle counter is connected , while the output of the clock pulses is connected to the second input of the address counter and the first input of the OR element, to the second input of which the output of the frequency divider is connected. The drawing shows the structure-but-electrical circuit of the device for searching for pseudo-random sequences. The device for searching for pseudo-random sequences contains a low-pass filter (LPF) 1, multiplier 2, unit receive 3, shift registers 4 and 5, adder 6, threshold block 7 , generator PSP 8, synchronization confirmation block 9, detection trigger 10, Clock generator 11, frequency divider 12, switch 13, additional frequency divider 14, address counter 15, one-shot 16, arithmetically an adder 17, the block valves 18, the cycle counter 19, an OR gate 20 and the random access memory unit 21.

The proposed device works as follows. .

The input pseudo-random sequence after filtering in the low-pass filter 1 arrives at the multiplier 2 and the unit-by-element reception unit 3, in which ID the symbols of the received sequence are evaluated or not. the interval of the duration of one symbol, or at an interval of P times shorter, where P is an integer, depending on the required noise immunity value and accuracy of determining the signal delay. The values obtained are advanced in shift register 4 at the rate of their formation, from the outputs — the times of which are fed to the inputs; coincidence adder b.

The shift register 5 receives btg abacus of the local sequence, generated by the generator of the memory bandwidth 8 (at P counts on the element). Frequency :: Formation of a sequence with a generator of bandwidth 8 in the signal search mode is (k + 1) 1, where i m is a clock; frequency input sequence. The clock frequency of shift register 5 is respectively equal to P (K + l) i.

The formation of these frequencies is carried out as follows.

Clock generator 11. generates the frequency PKij, which is fed to one input of the SHSh 20 element directly and to the second through; frequency divider 12 to k times, -.

Element OR 20 performs frequency addition. The received signal is an hour, Totahs RK + C is fed through an open switch 13 to shift register 5 and frequency divider 14 times P, which form the clock signal (K + 1) 1 hp g controlling the generator PSP 8 ..,

Each time the samples are shifted in shift register 4, there is a shift of shborok in shift register 5, and between them there are RK shifts in shift register 5, each of which counts the number of matching bits of shift registers 4 and 5 in. coincidence adder 6. The result of the calculation, expressed in the binary code, is fed to the arithmetic adder 17, which is summed with the binary number from the valve block 18.

In the initial state, the cycle counter 19 blocks the passage of signals through the valve block 18, and the numbers coming from the match adder 6 directly through the arithmetic adder 17 are fed to an operational storage unit 21, which is stored in the memory cells of the address counter code 15. Frequency of code change coincides With the relative frequency of advancement of samples in shift registers 4 and 5 and. equal to Pktrt,, and the conversion factor of the address counter 15 is equal to the number of samples of the input signal on one period of the SRP, i.e. PN, where the number of elements of a pseudo-random sequence.

Thus, in the first cycle, the values of the mutual correlation of the segments of the input and reference sequences are recorded corresponding to different time delays. After recording all NP values, the address counter 15 generates a transfer pulse, which changes the state of the cycle counter 19 and it fails to write to the valve block 18. In this case, the numbers recorded in the operative storage unit 21 are fed to the arithmetic adder 17 again and again at the same address, etc.

The loop counter 19 defines the total length of the sequence segment over which the cross-correlation function is calculated.

For example, if the shift registers 4 and 5 contain p {, bits, and the conversion factor of the cycle counter 19 is equal to M, then the length of the segment is equal to them.

In the last M-m state, the loop counter 19 generates a detection signal for triggering detection 10 to enable the reception of information. The values of the cross-correlation functions coming from the output of the operational storage unit 21 to the threshold unit 7 are compared with the threshold in the case of which a pulse is emitted which turns the detection trigger 10 into the corresponding signal detection state. In this case, the one-shot 16 produces a short pulse, setting the frequency divider 14 to the initial state, and the switch 13 connects the frequency signal Plffl to the frequency splitter 14. The frequency divider 14 generates the clock frequency tni of the generator PSP 8, the phase of which corresponds to the value found.

Formed at the tempo of the received case the sequence of the generator generator bandwidth 8 demodulates the input signal in multiplier 2, the signal of which is integrated, and compares

with a threshold in the synchronization confirmation block 9.

If the threshold is not exceeded, the synchronization confirmation block 9 sets the address counter 15 and the cycle counter 19 to the initial state, and the detection trigger 10 converts to

state corresponding to the non-detection of the signal.

The technical and economic efficiency of a pseudo-random sequence finder is to increase the noise immunity when receiving a memory bandwidth with large bases.

Claims (1)

SEQUENTIAL SEARCH DEVICE. SEQUENCE OF KNOBS, containing at its input a series-connected low-pass filter, a multiplier and a synchronization confirmation block. of a low-voltage circuit, connected in series by the element-wise reception block, a first shift register and a coincidence adder, to which other inputs are connected. the outputs of the second shift register, a series-connected clock generator and a frequency divider, the output of which is connected to the first input of the switch and to the first input of the bit-wise reception unit, to the second input of which the low-pass filter output is connected, as well as a pseudo-random sequence generator (PSP), the output of which connected to the first input of the second shift register and the second input of the multiplier, and a threshold block, which is related to the fact that, in order to increase the noise immunity of the search, consequently, an address counter, a counter of cycles, a detection trigger, a single vibrator and an additional frequency divider connected in series to the valve block, an arithmetic adder and random access memory, as well as an OR element whose output is connected to the second input of the switch, the third input of which is combined with the input of the single vibrator , and the output is connected to the second input of the second shift register and the second input of the additional frequency divider, the output of which is connected to the input of the SRP generator, while nitep.ny output clock generator is connected to a corresponding entry _with Bloch RAM (8 ka, to additional inputs of which are connected respective outputs of the address counter, a first input of which is combined with a second input of the loop counter and the second input of the detection trigger and connected to the output verification unit synchronism, the second input of which is connected to the output of the detection trigger, the third input of which is connected to the output of the threshold block, the input of which is connected to the ... zapomi th | huge capacity unit and the inlet valve unit, the other input of which is connected the second output of the loop counter, the output of the clock generator is connected to the second input of the address counter and the first WMOs dy OR gate, to whose second input connected to the output of the frequency divider.