SU522547A1 - Discrete matched filter - Google Patents

Description

(54) DISCRETE AGREED FILTER

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The invention relates to digital optimal filters used in radio measuring technology, and in particular to digital devices designed for synchronization of radio communication systems.

Known discrete consistent filter containing a clock pulse, shift register and adder l.

However, the known matched filter I has a limited range in the 6th recurrent binary sequence. The aim of the invention is to expand the range of the recurrent sequence to be extracted.

To do this, a pseudo-random sequence generator, a delay polynomial register, a decoder, a switch and serially connected ones, a pulse generator and | element | OR, whose output is connected to the clock inputs of the shift register, the outputs of bits i of which are connected to the corresponding inputs of the switch, whose output is under the keys to the information input of the shift register and to the adder, the second input of which is connected to the pseudo-random sequence generator, the output of the Clock Generator | the internal inputs of which are connected to the register of the delay polynomial and the decoder connected to the input of the switch and the installation input of the pulse builder.

The drawing shows st | j ucturn j electrically filter circuit.

The discrete matched filter contains a clock pulse generator 1, a shift register 2, an adder 3, a pseudo-random sequence generator (PSP 4, a delay polynomial register 5, a decoder 6, a switch 7 and a sequence. I connected the pulse shaper 8 and the element OR 9 whose output connected to the clock inputs of the shift register 2, the outputs of the bits of which are connected to the corresponding inputs of the switch 7, the output of which is connected to the information input of the shift register 2 and to the adder 3, the second input of which not connected to the generator 4pc, while the output of the clock 1 is connected to another input of the element OR 9 and to the driver of the pulse train 8, the output of which is connected to the clock inputs of the generator 4pc, the installation inputs of which are connected to the register of the delay polynomial 5 and the decoder 6, connected to the input of switch 7 and setting the input of the pulse builder The filter works as follows: the filter can be divided into two modes: recording the input sequence symbol and comparing the code state Shift register 2 with the reference sequence.

Each clock pulse from clock generator 1 records or O input sequence and performs a shift operation, at this point the feedback of shift register 2 is turned off, and then the pulse generator 8 is started. At this, the character recording mode ends.

Next, the pulses from the imaging unit pulse pulses 8 arrive at the clock inputs of the shift register 2, the generator PSP 4 and synchronously start them. In this case, the shift register 2 operates in a ring mode, and the number of pulses in a burst is equal to the number of characters in the reference sequence and the number of bits in shift register 2. The pulse frequency in the burst must be greater than N c where f is the frequency of the clock pulses of the clock pulse generator 1 ,

As a result, the output of shift register 2 through switch 7 will have a sequence of characters recorded in shift register 2, i.e., input, and at the output of the generator bandwidth 4, the reference sequence.

The number of matching characters is counted by adder 3, and with the required number of the latter, a signal is generated at its output.

The compare mode ends at the next clock pulse, which will write the next character and restart the pulse shaper 8.

Thus, at each clock pulse, one character is recorded and the recorded input sequence is compared with the reference memory bandwidth.

The code structure and the length of the reference bandwidth is specified by a delay polynomial, which is stored in the register of the delay polynomial 5 and is a parallel potential

A special code that controls the inclusion of half adders between the bits of the SRP 4 generator.

The maximum length of the memory bandwidth is 2–1, where I is the number of bits of the memory bandwidth generator 4,

Hence, prohibiting the input of a half adder of the pth digit, we obtain a sequence of length - 1, etc. If necessary, changing the structure of the code without changing the length of the memory bandwidth, the half admitters switch between the 1st and the Ihth bits

5 Changing the length of the reference sequence entails a corresponding change in the size of the shift register 2 and the number of pulses in the bundle of the imaging unit 8. This operation is performed by the decryptor 6, the output signal of which, depending on the delay polynomial code, switches the outputs of the shift register 2 and sets the number of pulses bundle shaper 8.

Changing the code of the delay polynomial occurs at the signal Njfnp

Thus, the proposed discrete matched filter has a variable transfer function and, therefore, can receive and allocate binary SRPs of any length and code structure.

Claims (1)

1. Auth. St. USSR № 373893, MKI N O4 B 15 / OO. 1971 (prototype). g --- I 1 b. I I. G T, I x-Ch. II I