SU447835A1 - Digital matched filter - Google Patents

Description

This invention relates to radio.

Digital matched filters are known for receiving a composite signal, grouped into two types of blocks, containing shift registers, register writing circuits, and a clock generator.

However, using well-known filters to receive signals with a large base (several thousand or more), an equally large number of logic elements is required.

The purpose of the invention is to simplify the device by reducing the number of logic circuits. This is achieved by the fact that the filter is made according to a two-stage scheme with shift registers in each stage, between which an adder, limiters, multivibrators, and I and MI circuits are included.

Fig, 1 shows a functional diagram of the proposed filter,

The voltage of the sum of the signal and interference is gated by pulses of the clock pulse generator 1 in the AND 2 circuit and through the recording circuit

register 3 is written to shift register 4; generator 1 pulses are used for register 4 and forward pulses simultaneously,

Fig, 1 shows the function.

filter circuit for the case when a complex signal consists of five consecutive blocks of ones and zeros forming

code 10001, the Unit unit consists of six elementary positive and negative parcels forming the code 111100, Block zero consists of six elementary positive and negative parcels forming the code 000011,

Fig. 2 shows the stress plots for the case when the enlarged units of ones and zeros are fixed when the number of matches with respect to the corresponding

codes 111100 and 000011 are not less than five. Limiter 5 passes only the voltage greater than the sum of the same amplitudes of a certain number of pulses to the input of the adder b, and limiter 7 only passes a voltage smaller than the sum of the same ash1 of the specified number of pulses j to the input of the adder 6. Thus, at the output of the circuit And 8 there is a pulse corresponding to the enlarged unit of the unit, and at the output of the circuit And 9 - a pulse corresponding to the enlarged block zero.

The pulses from the outputs of circuits 8 and 9 start the waiting multivibrators 10 and 11, which do not react to the input pulses during the time of their generation of pulses and restoration. generation and recovery are chosen in such a way as to exclude the BOSMOS passing through the multivibrators 10 and 11 for several pulses with a frequency of the generator 1. Through the OR 12 circuit, the pulses of the fasting pack® for the advancement of information recorded in the shift register 13. From the output of the multivibrator standby 10, the unit pulses are written through the writing circuit 14 into the shift register 13. In the case of dialing the corresponding code, an output pulse occurs at the circuit output 15.

In Figure 2, the following are accepted.

designations: a - signal voltage and interference at the input of the circuit 2; b - pulses at the output of the generator of clock pulses 1 in pulses at the output of the circuit And 2; g - impulses at the output of limiters 3 and 7; e - ishulsy at the output of the waiting multivibrators 10 and 11; e - the pulses arriving at the input of the write circuit in the register 14, and - the pulses at the output of the AND circuit

SUBJECT OF THE INVENTION A digitally matched dd filter for receiving a signal from a rupPaedoGo into two types of blocks, containing shift registers, recording registers in the register, clock generator, and from | THAT, in order to simplify the filter, it is performed according to a two-stage scheme with a shift register in each cascade, with the tap of the first cascade register connected via a dryer in parallel to two limiting boxes M | each of which, through its own AND-controlled circuit, is connected to the input

waiting for a multivibrag, the output of one multivibrator is connected in parallel to the write circuit in the cascade shift register and to the OR circuit, the output of the second multivibrator is only to the OR circuit, which is connected to the advancing input of the shift register.