SU1432515A1 - Random process generator - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in the construction of simulation equipment for solving optimization problems for complex systems. The purpose of the invention is to increase the speed of the generator. The generator contains a clock pulse generator 1, an analog adder 2, two identical channels 3 forming a random process, each of which contains a control unit 4, a sensor 5 random numbers, a memory unit 6, registers 7.8, a frequency divider 9, a counter 10, a reversible counter 11, converters 12, 13 code-voltage, memory block 14, element 15, register 16, frequency divider 17, trigger 18, block 19 modulo-two adders. The goal is achieved through the introduction of new blocks with appropriate links. 1 hp f-ly, 2 ill. SL

Description

one

14325

; The invention relates to computing technology and can be used in the construction of simulation and simulation equipment for solving optimization problems of complex technical systems.

The purpose of the invention is to increase speed.

EA fig, 1 presents a structural with |; hema generator of a random process; figure 2 - block diagram of the block

board

The generator contains a generator 1 so if OBbix pulses, analog adder

, two identical channels 3 forming a random process, each of which contains a block of 4 controls, a sensor of 5 random numbers, a block of 6 pa-iliHTn, registers 7-8, a divisor of 9 frequencies, a counter 10, a reversible counter

1 ,, converters 12 and 13 code-voltage, memory block 14, I element 15, register 16J frequency divider 17, rigger-18, block 19 cyNJMaTopoB via

; 10 two.

I Control block 4 contains triggers 20-22, elements AND 23-24, counter 25, decoder 26, elements AND 27-30.

The generator works as follows.

 By the beginning of the next cycle, codes defining the parameters of the next pulse are recorded in the IP memory block, and the trigger | 18 is set to a random equipolarity; | ioe state. The previous operation cycle stops when the reversible counter 11 reaches zero state . The next pulse from the output of the frequency divider 17 at the output of the reversible counter 11 generates a pulse that sets the trigger 20 of the control unit 4 into a single state, as a result of which a single signal is generated at the third output of the unit 4, with which the amplitude, duration and period from memory block 6 and writing these codes to registers 7-8 and reversing counter 11, respectively. The first pulse after setting trigger 19 of block 4 to the first input of block 4 from the generator 1 pulse output is set to navlivaet null state 20 trigger unit 4, this point in time the trigger 21 is in a single state, whereby the pulses from the output of the generator 1 received at the first input of the unit 4, pass

152

through the element And 23 block 4 to the information input of the divider frequency 9. At the output of the divider 9, the frequency is formed by a sequence of pulses with a frequency determined by the code stored in register 7. For each of these pulses, the counter 10 increases its state by one, forming the next address of the memory block 14, and the code is read from the block 14 memory at the address set by the previous pulse from the output of the frequency divider 9 and the entry of this code into the register 16, the highest bit of which is set in accordance with the previously established state of the trigger 18.

The 12 and 13 code-to-voltage converters convert codes entered into register 16 into the voltage of an electrical signal at a scale determined by a code stored in register 8, with the polarity given by trigger state 18. Thus As a result of the sequential increase in the state of the counter 10 and the reading of all the cells of the memory block 14, the output of each channel 2 generates a pulse of the original form specified by the sequence recorded by the block of code memory 14 with the duration, amplitude and polarity determined by The condition of the registers 7 and 8 and the trigger 18, respectively. When the counter 10 reaches the maximum output of the element 15, a pulse is formed that sets the counter 10 to zero and the register 16, as a result, the output of channel 2 is set to zero. In addition, the pulse from the output of the element 15 goes to the third input of block 4, in which it establishes a single state of the trigger 22, as a result of which the pulses from the first input of the block 4 through the element 24 are allowed and sets the zero state of the trigger 21 which prohibits the passage of pulses to the fifth output of block 4,

The pulses from the output of the element 22 are passed to the first output of block 4, to the input of the counter 25, to the first inputs of the elements 27-230, while a successive increase in the state of the counter 25 occurs, the state of which is decrypted by decipher 3J

RATOR 26, as a result of which the passage of pulses through AND 27-30 elements is sequentially permitted. The pulse from the output of the element 30 sets the zero state of the trigger 20 of the block 4 and the counter 25, thereby prohibiting the generation of control signals until the end of the cycle.

On the first, second, and fourth outputs of the block 4, the generator generates three random numbers, each of which is distributed according to a given law, recording these numbers in the corresponding areas of the memory block 6 and setting the random state of the trigger 18.

In parallel with the described formation of a pulse at the output of channel 2 and the formation of parameters of the next cycle by pulses from the output of the frequency divider 18, the units are sequentially subtracted from the reversible counter 11, the initial code of which specifies the duration of the follow-up period of the pulses 3. The subtraction occurs until until the zero state is reached in the reversible counter 11, as a result of which a subsequent pulse from the output of the frequency divider 17 causes the output of the reversible counter 10 impulses ca signaling unit 4 forming the end of the next pulse repetition period. After a pulse arrives at the second input of unit 4, the described cycle of operation of channel 3 is repeated. Random impulse processes of both channels 3 are summed by analog adder 2, as a result of which a pulse process with random amplitude, duration, follow-up period, polarity and complex shape is formed at the generator output.

Claims (2)

1. A random process generator containing a clock pulse generator. The first channel of forming a random process that contains the first register, the control unit, the first output of which is connected to the Onros input of the random number sensor, the second bit output of the control unit dinene with the recording resolution input of the first memory block, the third output of the control unit is connected to the synchronization input of the second register, the first divider 15 frequency, counter, reversible counter, first converter code - voltage, the output of which is connected to the input of the reference voltage reference of the second converter code - voltage, characterized in that, in order to improve performance, the analog adder is entered into it, the second channel forming a random process, and in each channel entered. the second memory block, the element I, the third register, the second frequency divider, the trigger, the block of adders for two are given; moreover, the output of the clock generator is connected to the first input of the control unit and the input of the second frequency divider of each channel forming a random process, the output of the second divider the frequency is connected to the subtracting input of the reversible counter, the overflow output of which is connected to the second input of the control unit, the third input of which is connected to the input of the AND element, the zero reset inputs of the counter and the third register, three The output of the control unit is connected to the synchronization input of the first register and the read enable input of the first memory block, the information input of which is connected to the output of the random number sensor, the output of the first bit of which is connected to the information input of the trigger, the synchronization input of which is connected to the fourth output control unit, the fifth output of which is connected to the input of setting the division factor of the first frequency divider, the output of which is connected to the counting input of the counter, the read enable input of the second unit the memory is connected to the synchronization input of the third register, the upper information bit inputs of which are connected to the corresponding bit inputs of the third memory block, the bit address inputs of which are connected to the bit outputs of the counter and the inputs of the I element, the first information output the first memory block is connected to the information input of the second register, the output of which is connected to the information input of the first frequency divider, the second information output of the first, block is connected to the information input of the first the register, the output of which is connected to the information input of the second converter; the code is the voltage whose output is 514325 The output of the first channel of forming a random process and connected to the first input of an analog adder, the second input of which is connected to the output of the second channel of forming a random process the register, the lower information bit outputs of which are connected to the corresponding low bit information inputs of the first converter code - 15 voltage and with the first modulo two adders block whose output is connected to the first information converter's first bit converter code - voltage, the highest 20 bit information output of the third I register is connected to the second modulo block adder j two, the third I information output The first memory block I is connected to the information input 25 I of the reversible counter, the input of which is connected to the third output of the control unit. 2. Generator pop. 1, which differs from the fact that the control unit 30 contains three flip-flops, six elements And, a counter, a decoder, and, the direct output of the first flip-flop is connected to the input of the installation of 1 second 15-6 a trigger whose direct output is connected to the first input of the first element I, the second input of which is connected to the counting input of the first trigger and the first input of the second element I, the second input of which is connected to the direct output of the third trigger, the zero input of which is connected to the output of the third element And, the first input of which is connected to the first inputs of the fourth, fifth and sixth elements And, the output of the third element And is the first output of the block, the outputs of the fourth, fifth and sixth elements And form the second discharge output Loka, the direct output of the first trigger is the third output of the block, the output of the second element I is connected to the counter input of the counter, the output of which is connected to the input of the decoder, the outputs of which are connected to the second inputs of the third, fourth, fifth and sixth elements AND the output of the fourth element I is the fourth output of the block, the output of the first element I is the fifth output of the block, the counting input of the first flip-flop is the first input of the block, the information input of the first flip-flop is the second input of the block, the zero reset second th flip-flop coupled to the input for setting to 1 and the third flip-flop is a third input block. J g eight