SU385283A1 - ANALOG-DIGITAL CORRELATOR - Google Patents

Description

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The invention relates to specialized computing devices designed to study the multiple correlation properties of random processes and to simulate various correlation discriminators.

Correlated tori are known to contain an operative charger, registers, null-arcs, multiplication schemes, and averaging schemes. The disadvantages of the known devices include a number of limitations associated with the range of variation of the delay (the argument of the correlation function) and with the hardware complexity if it is necessary to calculate the correlation moments in arbitrary combinations.

In the above correlator, these disadvantages are eliminated due to the fact that the correlator contains a typed field, the outputs of which are connected to the inputs of logical multiplication units, and its inputs are connected to the first register, to the output 1M of zero-organs and to the outputs of logical multiplication units. The second register is connected to odd bit inputs, with zero-organs, and even ones - to the outputs of the previous random-access memory (RAM) bits.

The principle of operation of the delay system, applied in the described correlator, consists in drawing the delay due to the bypass time

given number To words oa-m ty. Thus, the value written into the bit word is read out through K clock cycles, and instead a new value is written, since the delay of the count value relative to the current one is equal to K quantization intervals. If the value read from the bit is immediately written to another bit of this word, then the values read from this bit

will correspond to the delay of the process on 2K quantization intervals, etc. Thus, it is possible to select a delay time equal to an arbitrary number of quantization intervals. In this case, the interval

quantization is equal to the memory access cycle z (Af z). With the number of bits of the storage device /, it is possible to provide delays for a group of simultaneously polled processes, while the total number of delays is ek

All group processes are equal to /.

In order to organize delays P of groups of processes, it is necessary to take time between consecutive readings of processes (to call on R words of RAM. Delays of each group of processes are obtained by circumventing the corresponding arrays of words that do not intersect. The quantization interval of processes in this case is increased by P times (D PZ), and delay band

for each f-th group of processes is equal to Ati kj-Af, where ki is the number of words traversable in the t-M array. Due to the high speed of modern storage devices, the frequency of quantizing the processes of the three group form of delays may remain high. The drawing shows the scheme of the proposed correlator. Sources of the investigated signals are connected to the inputs of null organs 1-3. The outputs of the null organs are connected with a dial-up field 4 and with the inputs of the odd bits of the register of the number 5. The register 5 and the RAM 6 are connected by two-way links so that the outputs of the bits of the register 5 are connected to the write inputs of the same-named bits of the RAM 5, and the inputs all bits of register 5, except those connected to nuler organs, are associated with the outputs of the previous bits of the accumulator. The outputs of register 5 are connected by a paraphase code with inputs of the register of 7 multipliers. The generator 8 of synchronization signals is connected to the registers, RAM 6 and counter 9. The overflow output of counter 9 is connected via a switch block 10 to the inputs of the bits of counter 9. The outputs of the multiplier register 7 are connected to the typing field 4. The pairs of inputs of logical multipliers 11-13 are connected to null-organ outputs and a 7-factor register through a dial pad. The outputs of the multiplication units are connected to averaging schemes 14-16. The device works as follows. The next countdown of input processes is performed on a pulse from generator 9, which also goes to counter 9, increasing the code stored in code by 1 and to drive 6, which receives the address of the next word from counter 9 and reads the information stored in it. The results of the conversion of input signals are received in the corresponding bits of register 5, and the rest of its bits receive signals from the previous bits of the accumulator. When each clock pulse is counted, the counter goes through the K states, after which the overflow signal returns to the initial state and starts a new counting cycle. In this case, from each bit of the accumulator, in each clock cycle, the information that was recorded on the / C clock cycles is read. In 1, t + 1, ..., () -th bit, the current process counts are recorded, and in any other bit, information read from the previous bit is recorded. So, at outputs 1, from + 1,., (// +1) -th 3p dvd of the register of the number will be the current quantized processes, at outputs 2, tf 2, ..., (/ t + 2) - The second bits are quantized processes delayed by 2K. cycles, etc. At the outputs m, 2m, ... (/ + 1), the bits will be quantized processes delayed by (m -1) / g cycles, register 5 is in the zero (canceled) state for some time during each quantization interval. In order to eliminate the associated error, when the multiplication of the multiplication is continuously performed, the contents of the bits of this reporter are transmitted to the register of the multiplier 7 by the generator 8 signal. On multiplication blocks that implement the logic circuit of unequal one-bit codes, they are generated by the set selected with the HELP 4 signals from zero-organs and signals from the register of 7 factors. As a result, after averaging on the outputs of circuits 14-16, a signal is formed: Hz, proportional to the selected correlation moment. To calculate moments of more than a second order, the outputs of some multiplication units can be fed to the inputs of other multiplication blocks through a set field. Increasing the number of delays and obtaining different delay steps is achieved by introducing several counters with switchable feedback and several multiplier registers. In this case, in each clock cycle, the corresponding register of multipliers and the counter are cyclically connected to the number register and address inputs of the accumulator. As a result, several non-intersecting arrays are bypassed. iB principle with a different number of words, which increases the number of delays obtained and makes it possible to set a separate delay step in each bypass loop. The device can be used in particular to obtain simultaneously delays by argument time and averaging time when analyzing non-stationary processes. The subject of the invention is an analog-digital correlator containing a random access memory connected to a pulse generator and an address counter with switchable feedback, zero-organs by the number of correlator inputs, first and second registers, logical multiplication blocks connected to averaging schemes, different the fact that, in order to determine the correlation moments in arbitrary oscillations and increase the range of variation of the delays, it contains a composable field, the outputs of which are connected to the inputs of logic blocks o, and its inputs are connected to the first register, to the outputs of the zero-organs, and to the outputs of the logic blocks of multiplication; the second register is connected to the first and each m-m bit inputs with nullrganes, and the others - to the outputs of the previous bits of the operational storage device.

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