SU1168966A1 - Processor for transforming digital signals into haar-like bases - Google Patents

Abstract

1. A PROCESSOR FOR CONVERSION OF DIGITAL SIGNALS BY HAAROOMED BASIS, containing n computational blocks, a synchronization unit, first and second groups of shift registers and P switches, characterized in that, in order to improve accuracy and expand the scope of application by processing input sequences of length Nk . | c2. .. n (- any positive integers, d - 1, and) samples, 1st (i 1, and) computing unit contains 2 (k; -1) delay elements, switch, k multipliers, k memory nodes, and adder , the output of the j-th (j 1, 2k; -3) delay element is connected to the input of the (j + 1) -ro delay element and () +1) -th information input of the switch,

Description

keys to the information input of the first shift register (- and subgroups of the first group, with i- and (, n) the output of the first group of the synchronization unit connected to the control inputs of the memory nodes and the switch of the ith computing unit, 1st output of the second group of the block synchronization is connected to the control input of the i -th switch, the first and second outputs of the synchronization block are connected respectively to the clock inputs and the write enable entries of the shift registers of the second group, and the input of the synchronization block is the processor start input.

2. The processor according to claim 1, about tl and reading teM | that the synchronization unit contains (p-1) keys, (I-1) radonibrators, f serially connected frequency dividers a delay element and a clock pulse generator, the output of which is connected to the input of the first frequency divider and to the first input i-ro (i 1, n -1) a key, the second input of which is connected to the output of the i-ro one-shot, the input of which is connected to the output of the (-tl) -th frequency divider, the output of the 1st key (i 1, ri-1) is (i + 1) -M output of the second group of the synchronization unit, the output of the (n-1) -th one-shot is the nth output of the second group of the synchronization unit, output the clock generator is the first output of the first group and the first output of the synchronization block, the output of the delay element is the second output of the synchronization block, the input of the start of the clock generator is the input of the synchronization block, and the input of the delay element is connected to the output of the nth frequency divider.

The invention relates to high tech equipment and radio engineering and can be used in digital communication systems for building data compression devices, digital filtering, image processing, in radar signal processing systems based on the fast orthogonal baseline conversion algorithm, when input sample size N k, kj. .. 1 (n, - any natural numbers, i 1, p. The purpose of the invention is to improve the accuracy of calculations and expand the scope by processing input-to-ng sequences of length ,, k2. ... n (where C is any natural numbers, i 1, h) samples. The processor is designed for a natural order of input data, the results of calculations are also obtained in a natural order, i.e., ordered by rows of the orthogonal transformation matrix. In accordance with the algorithm used above the input data sample, measured by the vector f of the dimension N, mc is the following transformation: F f H,. where F is the resulting transformation, H-NxN is the transformation matrix. The fast orthogonal transformation over the input arrays is based on a recurrent construction of Haar-like matrices of order N. Kk ..., kj .. Let AC, () is a square matrix that satisfies the hype.,;,., 2) where T is the sign of matrix transportation, 1. is a row vector of k units, A is a matrix composed of the last ones (k; -1) rows of the matrix Aj (j, 0) s, - a row vector of k, zeros, Conditions (2) are satisfied by the cosine transform matrix, the Fourier matrix, the discrete linear basis matrix and the Haar matrix, when k, is any natural number; Walsh matrices and oblique matrices 3. 11689 transformations (s1ap1-transformations) when k 2t, t is any natural number; Hadamard matrices when k; 4t, t is any natural number. As an example, several such matrices are given: a) Walsh, k; 2

where ® is the Kronecker product.

(7)

R,

R; R,

F f

The output array at the ith stage of the transformation is denoted by the vector f (,. ..kj,) - the elemental vector, which is the product

(eight)

f- f R / R,

R

n

Then (f "...) Is the vector obtained at the (i-l) -M stage of the transformation, and

(9)

R:

i-1

Thus, the transformation at each i-M (, p) stage reduced to multiplication of the vector fj., Ha matrix R, defined by the formula (4).

Multiplication of the vector fi, Ha matrix R is performed as follows.

The first kj k, -. ..k N (i). elements of f are divided by mj

 -g groups of k elements each

Each group of elements is multiplied by a matrix. The first element, obtained by multiplying the first group, the input vector by the first row of the matrix AIJ, is the first element of the output, vector. The subsequent (k -1) elements obtained by multiplying the first group of the output vector by the remaining (k (-l) rows of the matrix A. „., I.e. on the matrix l. Are elements of the output 1 vector f; Stage i-ro with numbers from (t + 1) to (t, + k; -1).

The first element obtained by multiplying the second group of the input vector by the first row of the matrix A ,, is the second element of the output vector f |. The subsequent (k; -1) elements obtained by multiplying the second group of the input vector by the remaining () rows of the matrix A. are elements of the output vector 66 Then H is an orthogonal Haare-like matrix of the order N k, ... kfl, and transformation (1) is represented as follows:

fj of the i-th stage numbered from (mv + k;) to - {mj -2k; -2), etc.

For calculations at each i-th stage, the first N (i) elements of the input vector f,;., The remaining elements of this vector are the final result of the transformation and do not participate in further calculations

FIG. Figure 1 shows a block diagram of a processor before converting digital signals on Haar-like bases; in fig. 2 and 3 — switchboard and synchronization unit circuits, respectively; on fit. 4 - timing charts of the synchronization unit.

The processor has information input 1, contains computational blocks 2, -2, switches 3, two groups 4 and 5, -5 shift registers, intended for ordering the computation coefficients by rows of the transformation matrix, synchronization unit 6, which synchronizes the operation of all units of the device . the computational block contains 2 (D-1) elements 7–7 connected in series (. delay, switchboard 8, k, multipliers 9, -9 (f., kj nodes 10, -10-1 memory and adder 11. The control input of the computing unit is connected to the control inputs of the nodes 10; - 10ijj of the memory and the switch 8. The output of the switch 3 is the information output of the processor 12. The node lOj (,) of the memory is designed to store (in binary form) the elements The j-ro of the matrix column A. and contains k, successively connected shift registers. The information output of the 1OJ memory node is Inen with the information input of the memory node 10j and the second information input j-ro of the multiplier 9. Controls the inputs of computational units 13, -13jj and switches 14, -14, clock inputs 15 and inputs 16 for recording the second group of records, shift registers are connected to corresponding to the outputs of the synchronization unit 6. The switch 8 for each clock cycle connects to its k, - k outputs, from () its information inputs as follows. On the first clock cycle, the information inputs from the first to the inclusive are connected to the outputs, on the second cycle - from

second through (k +1) -th, ..., to k, -th and .contact, inputs are connected from krro to (2kJ-1) -th.

5, FIG. 2 shows one of the possible implementations of the switch 8, where 17 | - 17. - the information inputs a 18, - 18. - the outputs of the switch 8, which contains k | the same switches 19, - 19 ,, each of which has k information inputs., and one output. Inputs (first to

k-th) switch 19 (connected

with the inputs of block 8 from the first to the kj-and

respectively. Switch inputs

nineteen

2 are connected to the inputs of block 8 with

second PB (.... The inputs of the last kj-th switch 19c; connected to the inputs of block 8 from k - ro to (2kj-1) -th Outputs of switches 19, - 19 | j. are connected respectively to outputs 18, - 18 block 8. The synchronization inputs of the switches 19k are combined and are the control input of the KOMi ator 8.

FIG. 3 shows the circuit of the synchronization unit 6, which contains a generator of 20 clock pulses, p dividers 21, - 21 frequencies, one delay element 22 (kn − 1) cycles, (n − 1) single vibrators 23–23, and (n − 1) keys 24, - 24p.- ,.

The clock generator 20 is synchronized with the sampling rate of the digital signals from the analog-to-digital converter that are input to the processor. The output of the clock generator is connected to the input of the first frequency divider 21, with the first information inputs of the keys 24j-24, with the outputs 13, and 15 of the synchronization unit. The outputs of the keys 241-24. are the outputs of the I3j-13 block synchronization.

The output of the first frequency divider 21 is connected to the input of the second frequency divider 21J and the output 14 of the synchronization unit. The output of the frequency divider 21. (, p-1) is connected to the input 0 of the next divider 21 and to the output 14 of the synchronization unit. The output of the frequency divider 21 „is connected to the output 14 of the synchronization unit via a single vibrator. In addition, the output of the divider 21; (, p-1)

through the one-shot 23 is connected to the second input of the key 24, -. ,, and the output of the one-shot 23.- to the second input

key 24

Output divider 21

dinen with the input element 22 of the delay of the output of which is connected to the output 16 of the synchronization unit.

The generator 20 generates clock pulses (TI) with a repetition period T and duration T / 2. The frequency divider 21j (n) divides the frequency of the input signal by k, i.e. pulses with a duration equal to the duration of the TI and a period of k times larger than the period of the input signal arrive at its output. A single vibrator 23 (, n-1) extends the duration of the input pulse T / 2 in 2k. time. Ie up to the value of k T. Key 2D- (, p-1) passes to the output a signal from its first input, if there is a pulse at the second input from the one-shot 23. You can use p-1 as keys 24, - 24

yawn elements I.

FIG. 4 shows the diagrams of the synchronization unit.

Figure 1 shows the clock pulses from the output of the generator 20 to the input of the frequency divider 214, the first inputs of the keys 24, -, and

13, and 15

to the synchronization block outputs ..

Diagrams 2 and 3 show the pulses at the outputs 14 and 14 of the synchronization unit, respectively, and diagrams 4 and 5 show the pulses at the outputs of the one-shot 23 and the key 24I, respectively.

The processor works as follows.

With a frequency of clock pulses, the samples of a discrete signal are received at the input of the first computing unit. On the k, th cycle at the input block

 "

and k, -th count S, appears at the first input of the switch, at the output of the first delay element and at the second input of the switch (k.-l) -A

and output (k-l) -ro

Si count

delay element 7, and at the kth input of the switch, the first count is S ,. This clock is connected to the information outputs of the switch 8, its first k, information inputs, the elements of the first row of the matrix arrive at the second inputs of the multipliers.

r

from the outputs of nodes

c memory, and the first inputs clever S | f with outputs

inhabitants - counts S, T €

switch. As a result, on the way out

adder first computational

V.

the block will receive the sum of 21 and S.

5 Ng (k -1) tact for information

the input of the first computational unit is received by (k) -th countdown, and the information inputs of the switch are from the second to (kj + 1) -A, from the outputs of the delay elements from the first to k, -and

respectively, the counts S | - S. At this time, its information inputs from the second to () th are connected to the information outputs of the switch,

5 to the first inputs of the mind (the S, -S, c outputs of the switch are sent to the second inputs, and the elements of the second row of the matrix A to the second inputs of the multipliers (a, outputs of the nodes 10, -10,

0 memory. The adder calculates the sum of the works that arrive at its information inputs in parallel. 1

7

v, 3

g- J

On the () -th cycle the first compution is i,,.

The literal block gives the sum Г а, -S-. I.

I0 -

On this basis conversion

0 k, first k) samples (S, -S) is terminated. The first of the kj calculated results through the switch 3, on at the k, -th step at the first output, goes to the second computational unit for subsequent calculations. For the remaining (k, -1) clocks, switch 3 is turned on for the second output and the rest (k.-1) calculated results, which are Haar-like basis conversion factors with numbers (t, + 1) in (ra, + k, -1 ), arrive at the input of the registers 4 shift of the first group. The following k, cycles, starting with

5 (2k,) - ro, the first computing unit performs the transformation on the basis of k, the next k input

counts (S - Sj), etc.

On the Nth cycle, the Nth is input to the input of the first output block.

0 countdown Block 2 calculates the sum

tf

which through re-mj switch 3

, arrives at the input of the second computational unit 2. Subsequent () cycles to the input of unit 2, the first (k, -1) samples of the next sample, made up of

N samples, and block 2's adder calculates the last (k, -1) conversion coefficients of the previous sample from (Nk (+2) -th to N-th), which through switch 3 is fed to the input of group 4 of shift registers. 2, calculates the first sum of the conversion from the first kj samples of the second sample. By this time, unit 4 is already completely filled with conversion factors from (t. + 1) to Nth. Therefore, a gate pulse is fed to the clock from this synchronization unit to input 16 the second group of shift registers, allowing the flow of conversion factors Entering from block 4 to block 5.

Thus, the group 4 shift registers (ready, starting from the next clock cycle, to accept the transform coefficients of the second sample of counts). The computing units 2 - 2 work in a similar way.

A gate pulse is supplied to the input 16 of the second group of shift registers when the shift registers of the first group 4j-4 are completely filled} 1, and the clock frequency at which the conversion factors are applied to the shift groups of the second group 5, -5 is fed to the input 15 , are successively transmitted to the second information input of the switch 3. The switch 3 connects its first information input to the output during the first k cycles after the N-th countdown arrives at the device input, and the first processor through output 12 e k transform coefficients. The next (N-k) clocks switch 3 connects to the output the second information input and through it the rest (N-k) conversion factors arrive at the device output.

Phage.Z

FIG. 2 GITshsht JETl fL KgK2-T.

Hg-h

t f

5+

l p

flii e.

,

lll rLJLTLJl ,,.

Claims (2)

1. A PROCESSOR FOR TRANSFORMING DIGITAL SIGNALS BY KHAAR-LIKE BASIS, containing η computing blocks, a synchronization block, the first and second groups of shift registers and P switches, characterized in that, in order to increase accuracy and expand the scope by processing input sequences of length N = k , K ₂ . .. k _p (where V; are any natural numbers, ί = 1, p) of samples, ι-th (i = 1, p) computing unit contains 2 (k; -1) delay elements, commutator, k ^ multipliers, kj memory nodes and adder, the output of the j-th (j = 1, 2k; —3) delay element is connected to the input of the (j + 1) -ro delay element and () +1) -th information input of the switch, (2) ^ -1) the information input of which is connected to the output of the 2 (k; -1) -th delay element, the j-th (j = 1, kj) information output of the switch is connected to the first information input of the j-th multiplier, the information output p -th memory node is connected to the information the input of the jth memory node and the second information input of the jth multiplier, the output of which is connected to the jth input of the adder, the first information input of the switch and the input of the first delay element of the first computing unit are combined and are the information input of the processor, the output of the adder of the 1st (v = 1, n-1) of the computing unit is connected to the information input of the ϊth switch. the first information output of which is connected to the input of the first delay element and the first information input of the switch of the (, + 1) -th computing unit, the adder output of the Λ-th computing unit is connected to the first information input of the r-th switch, the information output of which is the information output of the processor, the first and second groups of shift registers contain (n ^_ 1) subgroups in (k; -1) -k { ₊ , ..., k _{n of} successively connected shift registers in ι-th (ΐ = 1, η-1) subgroup information output j-th (j = 1, _{(lq-1) · kj +,.. ..} k h 1 Registers sdeige ΐ -th (ί = 1, I-1) subgroup of the first group is connected to the data input of the j-th shift register 1-th subgroup of the second group, the information output ((k;.. -1) ki +, .. to _i ) of the shift register ί -th (* = 1, η-2) subgroups of the second group is connected to the information input of the first shift register (<+1) of the second group of the second group, and the information output ((k _n -1) k _n ) th shift register of the (n-1) th subgroup of the second group is connected to the second information input of the h-th switch, the second information output of the ΐ-th (ί = 1, η-1) switch under SU, ι „1168966 keys to the information input of the first shift register of the tth subgroup. of the first group, while the ί-th (ί = 1, η) output of the first group of the synchronization block is connected to the control inputs of the memory nodes and the switch of the <computational block, the ι-th output of the second group of the synchronization block is connected to the control input of the 1st switch , the first and second outputs of the synchronization block are connected respectively to the clock inputs and the inputs for recording the shift registers of the second group, and the input of the synchronization block is the input of the processor start. 2. The processor according to claim 1, wherein the synchronization unit contains (p-1) keys, (P-1) single-vibrators, and frequency dividers connected in series, a delay element and a clock generator, the output of which is connected to the input of the first frequency divider and to the first input of the ί-th (ϊ = 1, n ~ 1) key, the second input of which is connected to the output of the ί-th one-shot, the input of which is connected to the output of the (<+1) -th frequency divider, output ι-th key (i = 1, n-1) is the (ϊ + 1) -Μ output of the second group of the synchronization block, the output of the (n-1) -th one-shot is the I-th output m of the second group of the synchronization block, the output of the clock generator is the first output of the first group and the first output of the synchronization block, the output of the delay element is the second output of the synchronization block, the start input of the clock generator is the input of the synchronization block, and the input of the delay element is connected to the output of η frequency divider.