SU959092A1 - Multichannel statistic analyzer - Google Patents

Description

(54) MULTI-CHANNEL STATISTICAL ANALYZER

The invention relates to computational and measurement techniques and can be used to analyze random processes.

The known statistical analyzer contains two analog-digital converters, a synchronizer, a shift register, two decoders, a scaling circuit, a multiplier, four switches and two groups of accumulators, in which the estimates of the correlation functions, one-dimensional and two-dimensional, are calculated.

However, a large amount of equipment and the sequential calculation of the correlation functions of random signals reduce the speed of the device.

A statistical anashizator is known, containing two analog-digital converters, a synchronizer, storage cells, a shift register, correspondence decoders, binary, counters, decryption matrices, adders, limiters, matching circuits, and I and three groups of accumulators that have a greater speed when calculating correlation functions.

The disadvantage of the analyzer is a large amount of equipment.

The closest technical solution to this invention is a multichannel statistical analyzer containing first and second analog-to-digital converters, whose information inputs are device inputs, a generator

10 pseudo-random numbers, the first and second digital discriminators, the first inputs of which are connected to the outputs of the first and second analog-to-digital converters, respectively

15 second inputs - to the output of a pseudo-random number generator, a counter, a third digital discriminator, the inputs of which are connected to the outputs of the second analog-to-digital converter

20 and the counter, the switch, the matrix decoder, the inputs of which are connected to the output of the first analog-digital converter with the output of the switch, the first shift register, which is connected to the output of the first digital discriminator, and the parallel inputs of bits are connected to The outputs of the matrix decoder, which stores the cell,

30 input of which is connected to the output of the second digital discriminator, de: corresponding encoders, the first inputs of which are combined and connected to the memory cell output, and the second inputs are connected to the output of the corresponding bit of the first shift register, the drives whose inputs are connected to the output of the corresponding decoder corresponding , the second shift register, whose input is connected to the output of the third digital riminator disk, and the output to the switch input, the synchronizer, the outputs of which are connected to the control inputs (on digital converters, shift registers, a storage cell, a switch, and a counter 3. The disadvantage of this analyzer is a large amount of equipment due to the presence of AND accumulators (n is the number of ordinates of the correlation function). The purpose of the invention is to simplify the device. a multichannel statistical analyzer containing first and second analog digital converters, whose information inputs are the first and second inputs of the analyzer, respectively, and the control inputs. The first and second analog-digital converters are combined and connected to the first output of the control unit, the second output of which is connected to the counter input of the counter, and the third output of the control unit is connected to the control input of the first switch, the information input of which is connected to the output of the shift register, controlling the input of which is connected to the fourth output of the control unit; informational input - to the output of the first discriminator, the first input of which is connected to the output of the first analog-digital converter, non-random number generator, output. which is connected to the first input of the second discriminator, the second input of which is combined with the input of the matrix decoder and connected to the output BTOjioro of the antiscale digital converter, introduced the second commutator, frequency divider, start key and Computing blocks, Each of which consists of the input The MjfvraTopa com, the delay register, the multiplier and memory counter, the output of the second analyzer switch is connected to the second, the input of the first discriminator, and the first and second inputs are connected to the outputs respectively a pseudorandom number generator and a counter; the output of the second discriminator is connected to the first information. input input switch of the first computing unit, the second information input of the input switch of the i-th (i 1, 2, ..., k) computing unit is connected to the output of the higher bit of the delay register, to the first input of the multiplier of its computing unit and to the first the information input of the input switch (i + 1) of the number block, the output of the input switch of each i-ro computing unit is connected to the input of the first digit of the delay register of its block, the bit inputs of the delay register of the i-ro computing unit connected to the i-th output group of the matrix decoder, the output of the first analyzer switch is connected to the second input of the multiplier of each computing unit, the output of the multiplier of the 1st computing unit is connected to the counting input of the counter of its block, the discharge inputs and outputs of this counter are connected respectively to the outputs and the memory inputs of its block, the control inputs of the input switches all to the computing blocks are combined with the control inputs of the recording start key and the frequency divider and the connection to the fourth output of the control unit, the output of the frequency divider is connected to the input of the control unit, the fifth output of which is connected to the control inputs of the delay registers of all X. computational units, and the sixth output - to the control inputs of the memory of all k computational units, output The start recording key is connected to the information input of the frequency divide and to the reset inputs of the counters of all “computational units. The control unit consists of an AND element, a cycle trigger, the direct output of which is connected to the first inputs of the first, second, third and fourth elements AND, the second inputs of the first, second and first inputs of the fifth elements. And they are combined and connected to the first output of the pulse former whose input is connected to the output of the pulse generator, and the second output is connected to the counting input of the address counter, the input of the frequency divider and the second inputs of the third and fourth elements AND, the outputs of the first, second and third elements AND are the corresponding Essentially the fifth, fourth, and first outputs of the block, the inverse output of the cycle trigger is connected to the reset input of the address counter, the bit outputs of which are connected to the first inputs of the corresponding elements EXCLUSIVE OR and the inputs of the element OR NOT, the output of the higher address counter of the counter is connected to zero input of the trigger of cycles, with a single input of the trigger of memory reset and the counting input of the output counter, the reset input of which

combined with the third input of the fourth element AND, the second inputs of the EXCLUSIVE OR elements and connected to the inverse output of the output trigger, the single input of which is the input of the block, and the zero input combined with the zero input of the memory reset trigger, the counting input of the counter for. is connected to the high-output output of the output counter and is the second output of the block, the second input of the fifth element I is connected to the direct output of the memory reset trigger, the output of the delay counter is the third output of the block, and the outputs of the EXCLUSIVE OR of the fourth and The five elements of AND are the sixth output of the block, while the output of the element OR is NOT connected to the third outputs of the second and third elements AND, and the single input of the cycle trigger is connected to the output of the frequency divider.

FIG. 1 shows the structural scheme of the multichannel statistical analyzer; in fig. 2 - functional diagram of the analyzer control unit.

The first and second inputs 1 and 2 of the analyzer are the inputs of the first and second analog-digital converters 3 and 4, respectively. The output of the first analog-digital converter 3 is connected to the first input of the first digital discriminator 5, the second input of which is connected to the output of the second switch 6. The second analog-to-digital converter 4 is connected to the input of the matrix 1 de de scrambler 7 and to the first input of the second digital discriminator 8, the second input of which is connected to the first input of the second switch bis output generator pseudo-random numbers 9. The output of the first digital discriminator 5 is connected to the information input of the shift register 10, the output of which is connected to the information input of the first switch 11, the output of which is connected to the second inputs of multipliers 12 all K of the computation units 13. The output of the second digital discriminator 8 is connected to the first information the input of the input switch 14 of the first computing unit. 13. The second information input of the switch 14 of the I-th computing unit 13 is connected to the first input of the multiplier 12 of this block, with the output of the higher bit of the register 15 delay of this block and connected to the first information input of the input switch 14 (i + 1) of the computing unit 13 The outputs of the matrix decoder 7 are connected to the bit inputs of the delay registers 15 of the corresponding computing unit 13. The output of the multiplier 1-2 is connected to the counting input of the counter- 16, the bit

the inputs and outputs of which are connected respectively to the outputs and inputs of the storage device 17, the First output 18 of the control unit 19 is connected to the control inputs of the analog-digital converters 3 and 4, the second output 20 of the control unit 19 of the connection ;, and the counter input of the counter 21 whose output is connected to the second input of the second switch b, the third

0, the output 22 of the control unit 19 is connected to the control input of the first switch 11, the fourth output 23. with the control inputs of the input commutators 14 of all computational blogs

5 cocks 13, with the control input of the delay register 10, with the input of the start key 24, and with the information input of the frequency divider 25, the control input of which is connected to the Reset Inputs

0 counters 16 computing units 13 and connected to the output of the key 24 to begin recording. The output of frequency divider 25 is connected to the input of control unit 19, the fifth and sixth outputs 26, and

e 27 of which are connected to the control inputs of the delay registers 15, respectively, and jamming of the devices 17 of the computation units 13,

Pr my exit trigger cycles 28

connected to the first inputs of the first.

second, third and fourth ele. And 29, 30, 31 and 32, the second inputs of the first and second elements And 29 and 30 are connected to the first input of the fifth element and 33 and to the first output of the driver 34, the input of which is connected to the output of the pulse generator 35, and the second output is connected to the counting input of the address counter 36, the input of the frequency divider 37 and to the second inputs of the third and fourth elements And 31 and 32, the outputs of the first, second and third elements And 29, 30 and 31 are the fifth, quarter and first outputs of block 26 , 23 and 18. Inverse trigger output of cycles 28 is connected to INPUT1U scatter address counter 36, The discharge outlets are connected to the inputs pervo4 soofvetstvuyuschih ISKLYUCHEAYUSCHIE OR elements 38 and to the inputs of OR-NO element 39, the output of the most significant bit counters; address 36 is connected to the zero input of trigger cycles 28, to the single input of the memory reset trigger 4.0 and the counting input of the output counter 41, whose INPUT reset is combined with the third input of the fourth element And 32, the second inputs of the elements:;, EXCLUSIVE OR 38 and connected to inverse

the output of the output trigger 42, whose single input is the input 43 of the block, and the zero input is combined with the zero input of the memory reset flip-flop 40, the counting input of the delay counter 44,

Claims (3)

It is connected to the high-end output of the counter of output 41 and is the second output of the block 20, the third output 22 to which is the output of the counter of charge 44, and the outputs of the elements EXCLUSIVE THE SALTING OR 38, the fourth and fifth elements AND 32 and 33. The sixth output 27 of the block, the second input of the fifth element AND 33 is connected to the direct output of the memory reset trigger 40, the output of the OR-NOT 39 element is connected to the third input of the second and third elements 30 and 31, and the single input three heroes cycles 28 is connected to the output of frequency divider 37. The operation of the control unit is enclosed in impulses that set the mode of operation of the entire analyzer. Pulse generator 35 generates rectangular pulses, from I OTOPHX driver 34 produces two time-shifted pulses T1 and T2. The pulses T2 arrive at the counting input of the counter of address 36 and through frequency divider 37 to the single trigger input of cycles 28. Frequency divider 37 is connected to a switch (not shown) and sets the duration of the discrete delay step At. The counter 36 in each cycle outputs EXCLUSIVE OR 38 to the outputs 27 of the control unit, the address of the j-th memory cell, and in the computing mode, the address is output in the inverse form, and in the output mode - in the forward mode. The output mode is set by the trigger of output 42, which sets the pulse splitter 25 to the single state with an output pulse, which is fed to the control unit block 43. In each cycle, the trigger of cycles 28 is set to one state of pulses from the output of frequency divider 37. In the zero cycle of each operation cycle, which is specified by the OR-NOT 39 element, the outputs 23 and 18 of the control unit receive clock pulses through the elements 30 and 31, respectively T1 and T2. At the output 26 of the control unit, clock pulses T1 are output in each clock cycle. Simultaneously, in each clock cycle, a pulse 72 / corresponding to the write pulse of the memory devices 17 and a pulse Tlf corresponding to the read pulse are output through the I-32 and 33 elements. At the end of the t-th cycle of operation, the pulse from the output of the higher bit of the address counter 36 throws the trigger 28 of the cycle 28 to the zero state, which prohibits the passage of pulses through the elements 29, 30.31 and 32 until the next cycle, i.e. before entering a single trigger input 28 of the pulse from the output of frequency divider 37. in output mode trigger 42 prohibits the passage of write pulses (T2) to output 27 of the block, which allows storing information in memory devices 17 until the beginning of the next calculation step. Upon termination of the output mode from the output of the last discharge of the output counter 41, a pulse is applied to the output 20 of the control unit, the triggers 42 and 40 are reset to the counting input of the delay counter 44 and the read pulse ( r) through the element AND 33, so that zero information is entered into the counters 16, which is equivalent to resetting the contents of the memory cells 17. The memory reset trigger 40 is set to one state of the pulses from the output bit of the address counter 36. In the two-dimensional distribution laws computation mode, the delay of the second signal is changed automatically by pulses from the output 22 of the control unit. The device operates in five modes. The first mode. Calculation of estimates of correlation functions in real time using the sign method using auxiliary signals. Calculations of estimates of correlation functions are performed sequentially and in parallel over N cycles (where N is the amount of sampling used). The pulse period at the outputs 28 and 23 of the control unit 19 is equal to the pitch delay & f. The shift register 10 operates in the sequential shift mode of information coming from the output of the first digital discriminator 5. At the inputs 1 and 2 of the analyzer, random probes X (t} and y (t) are transmitted to the researcher, which are converted into a BINARY code with analog-digital converters 3 and 4. Digital discriminators 5 and 8 compare the codes given by converters 3 and 4, with codes from the pseudo-random number generator 9. At the same time, the first digital discriminator 5 generator code 9 is fed through the switch 6. Digital discriminators 5 and 8 give a logical unit if the code of the input signal is greater than the code of the auxiliary signal, and logical zero otherwise. The military sequence from the output of the digital discriminator 5 through the first bit of the shift register 10 and the switch 11 is fed to the first input of multipliers 12 computational units 13, and the other is a binary sequence from the output of the digital discriminator 8 to the first information input of the first switch 14. block .13, Each calculation cycle consists of m cycles (m is the number of bits of the delay register 15). In the first cycle, the write input from the input switch 14 is supplied with a write signal from the output 23 of the control unit 19, which is also fed to the control input of the shift register 10. At the same time, the first clock pulse from the output 26 of the control unit 19 is supplied to the delay registers 15. Through the input switch 14 to the first bit of the register 15, the delay of the first computing block 13 enters information from the output of the second digital discriminator 8. For the first bit of the register 15, the delay of the (i + 1) -th computing unit 13 in the first cycle of each cycle records information from the output of the higher t-th bit of the register 15 of the delay of the 1st computing unit 13 through the input switch 14. To the control inputs of the storage device 17 from the output 27 of the control block 19, the address code of the th cell ti, information from The multiplier 12 multiplies the value of the delayed sequence of pulses from the output of the old 15th delay register register with the value of another sequence of pulses fed to the multiplier 12 from the output of the first register register 10 shift through the switch 11. If both sequences coincide; a unit is fed to the counting input of the universal counter 16, which is added to the contents of the counter. The obtained value of the partial result i of the ordinate of the correlation function is entered in the tth cell of the memory device 17. In the J-OM (j O, 1, 2, ..., t-1) operation cycle for the first time, the delay register 15 is through switch 14, the value of the information from the 1 st input of the tth most significant bit of this register is entered into counter 16 — the value of the partial result (im-j) -th ordinate of the correlation function from the (mj) memory cell 17. In the storage Devices 17 in the form of n points equidistant along the argument with the step L / S accumulate the values of ki correlation function Rxy (-cr). . At the beginning of the calculation, the counters 16 are reset by the reset potential, which comes from the output of the start key of the record 24. The frequency delimiter 25 is also reset by the same potential. To eliminate the computation error during n cycles, the counters 16 and frequency divider 25 are in the zero state until all bits of the registers 15 of all computing blocks 13 are filled with pulse sequence values corresponding to the implementation X (t) under study. At the end of the nth cycle, the potential drop is removed and the evaluation of the correlation function begins. The input of the frequency divider 25 receives recording pulses from the output 23 of the control unit 19. The frequency divider has a division factor of 24 (d is the number of bits of the uyiver-sal counter 16) and when it overflows, a signal to the end of the calculation is sent to the input of control unit 19 and the output mode of the correlation function estimate starts. Second mode. Calculation of estimates of the integral law of distribution F (X) of a random process X (t). The calculation of the estimates F (X) is performed in parallel over N cycles. The delay registers 15 operate in parallel recording mode, and the shift register 10 is set to one, which does not change during the measurement process F, (X). The estimate of G (X) accumulates in memory devices 17 in the form of 2 n (p is the number of bits of the analog-digital converter) points equidistant along the argument axis with a step UX equal to the quantization level of the converter 4. Obtaining F {Xjt) is provided by decoder 7 in accordance with the ratio and /. .-, (AX / 2;, (o1Vhx.x (t) (/ 4) At the corresponding output of the decoder 7, a single signal is received to the corresponding bit of the shift register 15 and through the corresponding multiplier 12 to the counting input of the counter 16. Thus Thus, in the memory cells of memory devices 17, after N averaging cycles, an estimate of n points of the integral distribution law F (X) was obtained. Third mode. Calculation of estimates of the differential law of the w / X distribution of random process X {t). This mode differs from the previous one matrix decoder 7, which In this case, it works in accordance with the ratio and (4 4-1 i LX / Lx.x.)) (- (dX / 2; or “X (t) X 4uX / i; in memory devices 17 pos. N cycles averaging, the estimate of 2 n points of the differential distribution W (X) is obtained. Fourth mode. Calculation of the estimate of the integral two-dimensional distribution law F (X; Y; tr) of random processes X (t) and y (t). Estimate F (X; Y; T) are obtained in the form of estimates of 2 n points of section on X at ViSk-. S-V ,,, t comst, where i-. O, l, 2, ... (2-1) - sogo; counter count 21; t О, 1, 2, .. ,, L is the bit number and the register of 10 shift. The period of the pulses at the output 22 of the control unit 19 of the port T9f-H utja NiTf ©, where & - the time of withdrawal of all assessment points from the storage devices 17 and their resetting. The pulse period from the output 20 of the control block 19 is equal to Atuo. The calculation of the F (X; y; Tr) estimates is performed in (in + 1) steps / in each of which the estimate F. (X; Y; T) is found at all values of X and but for one specific value of m EDT, varying in steps with shifts & t. The transition from one stage to another, i.e. the change of the argument T i of the center (it is auto-controlled, using the switch 11, by the pulses from the output 20 of the control unit 19. The shift register 10 and the collider 11 can change the tr in the range from O. with steps of DEM. The next step consists of n substep in from which {wx is estimated F (X; Y; C) points that are evenly spaced along the X-axis through HH, when YY is copsi, t TM "const, where UI is the code value of the input signal Y () when n -th state of the counter 21, The transition from one substage to a dynamic, i.e. a change in the level of analysis y (t) is driven by pulses from the output 22 of the control lock 19. Each sub-stage consists of N cycles of the same duration as the cycles of calculating the correlation.In each cycle, the matrix 7 from converter 4 is given the signal code X (t); Digital discriminator 5 operates in the same direction as the decoder 7. The actuation level of the discriminator 5 is set by the counter 21. The matrix decoder 7 and the discriminator 5 operate in accordance with a relation similar to the second one. Over .N cycles the estimate is calculated. F {X, yjt) of the integral two-dimensional law of the distribution of random signals X (t) and y (t) in the form of n points equally spaced in the argument X with step L X at Y 3, -fc (n-1) AT. Nevertheless, the sections of the estimate F (X; Y; T) are obtained successively in time T Atao L () L-l. Fifth mode. Calculation of estimates of the differential two-dimensional distribution law W (X; VjC) of random processes X (t) and y (t). This mode differs from the previous one in that the decoder 7 and the discriminator 5 operate in. according to a ratio similar to the third mode. Thus, this analyzer requires less hardware, since measurements of several characteristics of random processes are carried out on the same equipment and the number of accumulators and decoders of conformity is reduced. The analyzer allows you to measure the characteristics of random processes in real time. Claim 1, A multi-channel statistical analyzer containing first and second analog-to-digital converters, whose information inputs are in-: the first and second inputs of the analyzer, respectively, and the control input of the first and second analog-to-digital converters are combined and connected to the first output of the control unit , the second output of which is connected to the counter input of the counter, and the third output of the control unit is connected to the control input of the first Switch, whose information input is connected to the output of the shift register, the control input of which is connected to the fourth output of the control unit, and the information input to the output of the first discriminator, the first input of which is connected to the output of the first analog-digital converter, a pseudo-random number generator, the output of which is connected to the first input of the second discriminator ra. the second input of which is combined with the input of the matrix decoder and connected to the output of the second analog-f digital converter, characterized in that, for the purpose of simplification, it contains a second switch, a frequency divider, a recording start key and If computing blocks, each of which consists of an input switch , the ator, the delay register, the counter, the multiplier and the storage device, with the output of the second analyzer switch connected to the second input of the first discriminator, and the first and second inputs to the outputs, respectively, of the generator pseudorandom numbers and a counter, the output of the second discriminator is connected to the first information input of the input switch of the first computing unit, the second information input: the input switch of the 4th (1, 2. K) computing unit is connected to the output of the higher bit of the delay register , with the first input of the multiplier of its computing unit and with the first information input of the input switch (i + 1) -th computing unit, the output of the input switch of each i -th computing unit is connected to the input for the first time A row of the delay register of its block, the bit inputs of the delay register of the 4th computing block are connected to the i group of outputs of the matrix decoder, the output of the first analyzer switch is connected to the second multiplier input of each computing block, the output of the multiplier -f-ro computing block is connected to the counting input of the counter of its block, the bit inputs and outputs of this counter are connected, respectively, with the outputs and inputs of the memory of the device of its block, the control inputs of the input commutators of all to calculate The new blocks are combined with the control inputs of the start key and frequency divider and connected to the fourth output of the control unit, the output of the frequency divider is connected to the input of the control unit, the fifth output of which is connected to the control inputs of the delay registers of all K computational blocks, and the sixth the output is with the control inputs of the memory devices of all computational units, the output of the start recording key is connected to the information input of the frequency divider and to the reset inputs of the counters of all k computational units. .. 2. The analyzer of claim 1, wherein the control unit consists of AND elements, a cycle trigger, the direct output of which is connected to the first inputs of the first, second, third and fourth AND elements, the second inputs of the first, second and first inputs of the first elements I are combined and connected to the first output of the pulse former, the input of which is connected to the output of the pulse generator, and the second output is connected to the counting input of the address counter, the input of the frequency divider and the second inputs of the third and fourth elements And exits first o, the second and third elements AND are the fifth, fourth and first outputs of the block respectively; the inverse output of the cycle trigger is connected to the reset input of the address counter, the bit outputs of which are connected to the first inputs of the corresponding elements EXCLUSIVE OR and the inputs of the element OR NOT, In this case, the high-order output of the address counter is connected to the zero input of the cycle trigger, to the single input of the memory reset trigger and the counting input of the output counter, the reset input of which is combined with the third input of the fourth element And, second 4 and the inputs of the items EXCEPT OR or connected to the inverse output of the output trigger, the single input of which is the input of the block, and the zero input is combined with the zero input of the memory reset trigger by the counting input of the delay counter, connected to the output of the higher discharge counter of the output counter and is the second output unit, the second input of the fifth element And is connected to the direct output of the memory reset trigger, the output of the delay counter is the third output of the block, and the outputs of the elements EXCLUDING OR, the fourth and fifth elements AND are the sixth in stroke unit, wherein the output element is connected to Ilin third outputs of the second and third AND gates, and a single trigger input connected to the output of the frequency divider cycles. Sources of information taken into account during the examination 1. USSR author's certificate 364944, cl. G 06 F 15/36, 1973. 2. USSR author's certificate number 383057, cl. G 06 F 15/36, 1973. 3.Avtrokoe certificate of the USSR №732890, cl. G 06 F 15/36, 1980 (prototype). city / ue