RU2116670C1 - Information search engine - Google Patents

Abstract

FIELD: computer engineering, in particular, search of determined combinations in information array. SUBSTANCE: device has generator of current estimations, discriminator of estimation value regions, pulse distributor, counter of time intervals, first and second generators of search variable, first and second adding counters, first and second memory units, divider, classifier, search strategy register, reset signal generator, indicator, threshold signal measuring unit, day timer. Device provides analysis of input flow and detection of determined combinations in it, detection and counting of their presence or absence according to time of day, calculation of a posterior integral functions F_n(N) and F₀(N) and generation of plausibility ratio L(N) = F_n(N)/F₀(N), which value is then compared to threshold values П_clu and П_cll, which alter by means of generator of cut-off threshold according time of day depending on intensity of input flow. These data are used for making decision on environment condition according to Wald criterion. EFFECT: increased speed for given probability of correct choice. 5 cl, 11 dwg

Description

 The invention relates to the field of computer technology and can be used as a device for searching for deterministic combinations in an information array.

 A known analogue of the proposed device is described in ed. St. USSR N 1621049, class G 06 F 15/40, announced on 01/09/1989, and contains boundary registers that add up and subtract counters, comparison circuits, memory blocks, calculation blocks and a number of other elements that allow you to search for information. However, this operation is implemented in it with low efficiency.

 The nearest information retrieval device (prototype) to the proposed one is described in ed. USSR N 1711185, class G 06 F 15/40, claimed 05.04.89. The indicated invention describes an information search device comprising upper and lower bound registers, an adder-subtracter, a search strategy register, subtracting and adding up counters, comparison circuits, a memory block, a key register, an output register, groups of AND and OR elements, a trigger, a pulse distributor , launch input, upper and lower bound address inputs, input of the search strategy change criterion code, key input, address output, output of a sign of lack of information. The described device has a higher efficiency compared to the above.

 However, the prototype device implements the search for rare information blocks in the array using the dichotomous method, which is its drawback in the case of searches in the information array of combinations that have a high probability of occurrence, as search efficiency decreases.

 Indeed, the mathematical essence of the method of half division (dichotomy) is that, in order to determine some Δf (x) on the segment [a, b], the latter is halved and at its midpoint c = (a + b) / 2 is calculated value f (c). If f (c) = Δf (x), then for the subsequent halving, one of the following two segments [a, c] and [c, b], etc., is selected. (A.M. Prokhorov et al. Mathematical Encyclopedic Dictionary. M.: Soviet Encyclopedia, 1988).

где
K_тр - количество искомых блоков в массиве:
K_общ - общее количество блоков в массиве.The specified procedure is implemented in the already described device for finding the required information blocks in a certain array, provided:

Where
K _Tr - the number of blocks sought in the array:
K _total - the total number of blocks in the array.

Следовательно, можно представить:

где
T - общее время поиска в массиве;
γ - скорость поиска;
T_μ = T_{перестр.} + T_{анализа} - время, необходимое для анализа одного сектора.Let the length of the desired block be μ _tr . Moreover, μ _tr <μ, where μ is the length of the elementary analyzed implementation (analysis base) in an array of volume S. In this case, the number of search sectors K is determined (V.A. Abchuk, F.A. Matveichuk, L.P. Tomashevsky. Handbook of Operations Research, Moscow: Military Publishing House, 1979):

Therefore, we can imagine:

Where
T is the total search time in the array;
γ is the search speed;
T _μ = T _perest. + T _analysis - the time required to analyze one sector.

Т. е. указанное устройство - прототип требует значительных временных затрат при заданной вероятности правильного решения.For the dichotomous method:

That is, the specified device is a prototype requires significant time costs for a given probability of a correct solution.

 The aim of the invention is the construction of a device having a higher efficiency of information retrieval for a given probability of a correct solution. The object of recognition for the proposed device is the state of the situation based on the assessment of the input traffic, considered as an information array in which there are some deterministic code combinations (in this case, the combination of the beginning of the message — CNS). It is according to the SPS that the intensity of the input traffic and, as a result, the state of the situation are estimated. In the future, the designations “O” correspond to these states - there are no changes and “P” - changes are present. The decision on the state "P" is made in the case when the intensity of the input traffic deviates from the average value to a greater or lesser extent by an amount that exceeds the threshold, otherwise a decision is made on the state "O". In turn, the upper and lower thresholds can be either interval or point, which is determined by the search strategy adopted in the search device at this stage.

This goal is achieved by the fact that in the known information retrieval device including a pulse distributor, an adder-subtractor, which is essentially a generator of a search variable, a totalizing counter, a memory block and a search strategy register, a current evaluation signal generator, a discriminator of evaluation value zones, a counter are additionally introduced time slots, switch, second variable search driver, totalizing counter and memory block, division block, classifier, reset signal generator, in block pecifications, the block change threshold signals and the timer of the current day. The information inputs of the current evaluator signal generator and the discriminator of the evaluation value zones are combined and are the information input of the device. The first output of the pulse distributor is connected simultaneously to the synchronization inputs of the signal generator of the current estimation of the discriminator of the evaluation value zones, as well as to the clock input of the time interval counter, and the second, third and fourth outputs of the pulse distributor are connected respectively to the clock inputs of the switch, the first and second memory blocks and the classifier . The output of the current day timer is connected simultaneously to the “Time” inputs of a pulse distributor, a current estimator, a discriminator of the evaluation value zones and a threshold signal change unit, the outputs of which are the search thresholds “Pv” and “Mon” are connected to the same inputs of the search strategy register, the outputs the values of the upper and lower classification thresholds of which "P _cl to" and "P _cl n" are connected to the corresponding inputs of the classifier. The outputs of the classifier “P” and “O” are connected simultaneously to the corresponding inputs of the display units and the shaper of the reset signals, the output of which is connected simultaneously to the inputs “Reset” of the first and second memory blocks, the counter of time intervals and the search strategy register, whose input is “N _text ” connected to the output of the counter of time intervals. The output of the first driver of the search variable is connected to the first information input of the first totalizing counter, the second information input of which is connected to the output of the first memory block, and the output of the first totalizing counter is connected simultaneously with the information input of the first memory block and the first information input of the division block. The output of the division unit is connected to the information input of the classifier. The output of the second totalizing counter is connected simultaneously to the second information input of the division unit and the information input of the second memory block, the output of which is connected to the second information input of the second totalizing counter, the first information input of which is connected to the output of the second driver of the search variable, the information input of which is connected to the output "0 "switch, and the output" P "of the switch is connected to the information input of the first driver of the search variable. The inputs "N _max " of the first and second formers of the search variable, as well as the search strategy register, are connected simultaneously to the device input of the same name. The inputs "Zone 1" and "Zone 2" of the device are inputs of the "Zone", respectively, of the first and second formers of the search variable. The control input of the switch is connected to the output of the current evaluator signal generator, and the inputs of the switch "P" and "O" are connected to the corresponding outputs of the discriminator of the evaluation value zones. The inputs "Threshold" and "Start" of the device are connected to the inputs of the same name block changes the threshold signals.

 The current estimation signal generator consists of a decoder, first and second count coefficient encoders, first and second counters, as well as NOT and OR elements. The “Time” input of the shaper is the input of the decoder, and its output is connected simultaneously with the inputs of the first and second encoders. The signal from the outputs of these encoders is fed to the inputs of setting the account coefficients of the first and second counters, respectively, the counting inputs of which are connected simultaneously to the information input, and the clock inputs to the synchronization input of the shaper. The output of the first counter is connected to the first input of the OR element, the second input of which through the element does NOT receive a signal from the output of the second counter. The output of the OR element is the output of the shaper.

 The discriminator of the evaluation value zones consists of a decoder, counter, first, second, third and fourth encoders, first, second and third subtracters, first and second comparators, first, second and third keys, an OR circuit, and also the first and second division devices. The “Time” input of the discriminator is the input of the decoder, the output of which is connected simultaneously to the inputs of all encoders. The information input and the synchronization input of the discriminator are respectively the information and clock inputs of the counter, the output of which is connected simultaneously to the inputs of the reduced first subtracter, as well as the subtracted second and third subtracters, and to the information inputs of both comparators. The threshold input of the first comparator, the input of the subtracted first and the input of the decreasing second subtractors are combined and connected to the output of the first encoder. And the threshold input of the second comparator and the input of the reduced third subtractor are combined and connected to the output of the second encoder. The outputs of the third and fourth encoders are connected to the inputs of the dividend, respectively, of the first and second division devices, the inputs of the divider of which are connected respectively to the output of the second key and the output of the OR circuit. The outputs of the first, second and third subtractors are connected to the information inputs of the first, second and third keys, respectively, and the outputs of the first and third keys are connected respectively to the first and second inputs of the OR circuit. The outputs "<" of the first and second comparators are connected respectively to the first control input of the second and control input of the third key, and their outputs ">" are connected respectively to the control input of the first key and to the second control input of the second key. The outputs of the first and second division devices are respectively the outputs "P" and "O" of the discriminator.

The classifier consists of the first and second comparators and the first and second keys. The information inputs of the first and second comparators are connected simultaneously to the information input of the block, and their threshold inputs are respectively connected to the inputs of "P _cl in" and "P _cl n" of the block. The output ">" of the first comparator is connected to the information input of the first key, and the output "<" of the second comparator is connected to the information input of the second key. The control inputs of the keys are connected simultaneously to the clock input of the classifier, and the outputs of the first and second keys are respectively the outputs "P" and "O" of the classifier.

The register of the search strategy consists of the first and second registers, the first and second subtracters, the device of division by two, the comparator, the first, second and third keys, as well as the first and second OR circuits. The information input of the comparator is connected to the input "N _streaming ", and the threshold input is connected to the input "N _{max of the} search strategy register. The information inputs of the first and second registers are connected respectively to the inputs" Pv "and" Mon "of the search strategy register. The output of the first register is connected simultaneously with the inputs of the reduced first and second subtractors and the information input of the first key, and the output of the second register is connected simultaneously with the input of the subtracted first subtractor and the information input of the third key. the input of the divider by two, the output of which is connected to the input of the subtracted second subtractor.The output of the second subtractor is connected to the information input of the second key, the control input of which is connected to the output "≥" of the comparator. The output "<" of the comparator is connected simultaneously with the control inputs of the first and third keys the outputs of which are connected to the first inputs of the first and second OR circuits, respectively.The second inputs of the OR circuits are combined and connected to the output of the second key. The outputs of the first and second OR circuits are the outputs of the “Cl _key ” and “Cl _key ” of the search strategy register, and the inputs of the initial setting of both registers are connected simultaneously to the “Reset” input of the search strategy register.

Thanks to this combination of blocks and their connections, it is possible to reduce the total search time T at various percentages of K _Tr to K _total , provided that the probability of correct recognition is equal.

In FIG. 1 shows a general diagram of an information retrieval device; in FIG. 2 - signal conditioner of the current assessment; in FIG. 3 - discriminator of the zones of the evaluation values; in FIG. 4 - pulse distributor; in FIG. 5 - switch; in FIG. 6 - shaper variable search; in FIG. 7 - classifier; in FIG. 8 - search strategy register; in FIG. 9 - block changes in threshold signals; in FIG. 10 is a comparative graph of sequential and dichotomous information retrieval methods at K _Tr = (0.15-0.25) K _total ; in FIG. 11 is a comparative graph of sequential and dichotomous information retrieval methods at K _Tr = (0.80-0.90) K _total .

 The device shown in FIG. 1, contains a shaper 1 of the signals of the current assessment, a discriminator of 2 zones of evaluation values, a 3 pulse distributor, a counter 4 time intervals, a switch 5, the first 6 and second 7 shapers of the search variable, the first 8 and second 9 totalizing counters, the first 10 and second 11 blocks memory, division unit 12, classifier 13, search strategy register 14, reset signal generator 15, indication unit 16, threshold signal change unit 17, current day timer 18.

The information inputs of the driver 1 and discriminator 2 are combined and are the information input of the device. The first output of the pulse distributor 3 is connected simultaneously to the synchronization inputs of the driver 1, discriminator 2, and also to the clock input of the counter 4. The second, third, and fourth outputs of the distributor 3 are connected respectively to the clock inputs of the blocks 5, 10-11, and 13. The output of timer 18 is connected to the inputs "Time" of the shaper 1 and discriminator 2, the inputs of the distributor 3 and block 17, the outputs of "Pv" and "Mon" of the thresholds of which are connected to the corresponding inputs of the register 14. The outputs of the "P _CL " and "P _CL " thresholds classification register 14 connected to match the input inputs of the classifier 13, the outputs of which “P” and “O” are connected simultaneously with the corresponding inputs of the blocks 15 and 16. The information input of the classifier 13 is connected to the output of the division unit 12. The output of the reset signal generator 15 is connected simultaneously to the “Reset” inputs of counter 4, blocks 10-11 of the memory and register 14. The inputs "N _current " and "N _max " of the register 14 are connected respectively to the output of the counter 4 and the input "N _max " of the device. The output of the shaper 6 is connected to the first information input of the counter 8, the second information input of which is connected to the output of block 10. The output of the counter 8 is connected simultaneously with the information input of the memory unit 10 and the first information input of the division unit 12. Similarly, the connections of blocks 6, 8, 10 are connected and blocks 7, 9, 11 - the output of the shaper 7 is connected to the first input of the counter 9, the second input of which is connected to the output of the block 11, the output of the counter 9 is connected simultaneously with the information input of the block 11 and the second input of the block 12 divisions. The information inputs of the shapers 6 and 7 are connected respectively to the outputs of the switch "P" and "O", and their inputs "N _max " are combined and connected to the device input of the same name. The input "Zone" of the shaper 6 is connected to the input "Zone 1" of the device, and the input "Zone" of the shaper 7 is connected to the input "Zone 2" of the device. The control input of the switch 5 is connected to the output of the shaper 1, and the information inputs of the switch "P" and "O" with the corresponding outputs of the discriminator 2.

 The current estimation signal generator shown in FIG. 2, at the end of the current analysis interval, a binary signal is generated that characterizes the state of the situation. This signal, taking the values of "P" or "O", then arrives at the control input of switch 5. The shaper consists of a decoder 1.1, first 1.2 and second 1.3 count coefficient encoders, first 1.4 and second 1.5 counters, elements NOT 1.6 and OR 1.7. The input of the decoder 1.1 is the input "Time" of the shaper, and the output of the decoder is connected to the input of the encoders 1.2 and 1.3, the signal from the outputs of which goes to the inputs of the setting of the account coefficients, respectively, of the counters 1.4. and 1.5. The counting inputs of the counters are connected simultaneously to the information input of the shaper. The output of counter 1.4 is connected to the first input of the OR element, the second input of which through element 1.6 receives the signal from counter 1.5. The output of element 1.7 is the output of the shaper, and the input of the initial installation of counters is connected to the synchronization input of the shaper.

 In FIG. Figure 3 shows the discriminator of the evaluation value zones, which generates a signal about the zone number of the state in which the input stream of the corresponding intensity is located and consists of a decoder 2.1, counter 2.2, encoders 2.3, 2.4, 2.5 and 2.6, subtractors 2.7, 2.8 and 2.9, comparators 2.10 and 2.11, keys 2.12, 2.13 and 2.14, OR circuits, as well as division devices 2.16 and 2.17. The “Time” input of the discriminator is the input of the decoder, the output of which is connected simultaneously to the inputs of all encoders. The information input and the synchronization input of the discriminator are respectively the information and clock inputs of the counter, the output of which is connected simultaneously to the inputs of the reduced subtracter 2.7, subtracted subtractors 2.8 and 2.9, as well as to the information inputs of both comparators. The threshold input of the comparator 2.10, the input of the subtracted subtractor 2.7 and the reduced subtracter 2.8 are combined and connected to the output of the encoder 2.3. The threshold input of the comparator 2.11 and the input of the reduced subtractor 2.9 are combined and connected to the output of the encoder 2.4. The outputs of the encoders 2.5 and 2.6 are connected to the inputs of the dividend, respectively, of the division devices 2.16 and 2.17, the inputs of the divider of which are connected respectively with the output of the key 2.13 and the output of the OR circuit. The outputs of the subtractors 2.7, 2.8 and 2.9 are connected respectively to the information inputs of the keys 2.12, 2.13 and 2.14. The outputs of the keys 2.12 and 2.14 are connected respectively to the first and second inputs of the OR circuit. The outputs "<" of the comparators 2.10 and 2.11 are connected respectively to the first control input of the key 2.13 and the control input of the key 2.14, and the outputs ">" of these comparators are connected respectively to the control input of the key 2.12 and the second control input of the key 2.13. The outputs of the division devices 2.16 and 2.17 are respectively the outputs "P" and "O" of the discriminator.

 In FIG. 4 is a diagram of a pulse distributor designed to synchronize the operation of the entire device by forming four pulse sequences shifted relative to each other by a certain value Δt. The distributor consists of a decoder 3.1, a counter 3.2 and delay elements 3.3, 3.4, 3.5. The input of the pulse distributor is connected to the input of the decoder, from the output of which the signal is fed to the input of the counter. The counter output is connected to the input of the first delay element 3.3, the output of which is fed to the input of the second delay element 3.4, the output of which is connected to the input of the third delay element. The outputs of the counter, as well as the first, second and third delay elements are, respectively, the first, second, third and fourth outputs of the pulse distributor.

 The switch shown in FIG. 5, the signal of the zone number is inputted to the input of the corresponding driver of the search variable by the control signal coming from block 1 and receiving the value "P" and "O". The switch consists of two elements And 5.1 and 5.2 and the element NOT 5.3, the first inputs of the elements And 5.1 and 5.2 are respectively connected to the inputs "P" and "O" of the switch, the second to the clock input of the switch, the control input of the switch is connected to the third input of element 5.1 and the input of the element NOT 5.3, the output of which is connected to the third input of the element 5.2, the outputs of the elements And 5.1 and 5.2 are respectively the outputs of the switch "P" and "O".

Shapers of the search variable 6 and 7 (Fig. 6) are intended for constructing increments of posterior integral probability distribution functions of the normal F _o (N) (block 6) and the rejected F _p (N) (block 7) traffic state on the Nth observation interval. Since the circuits of the shapers 6 and 7 are identical, only the shaper 6 is shown here, which consists of a multiplier 6.1, the first and second inputs of which are connected respectively to the inputs “Zone” and “N _max ” of the shaper, as well as from the division device 6.2, to the input whose divider is fed the result of multiplication from the multiplier 6.1, and the input of the dividend is connected to the information input of the shaper. The output of the division device is connected to the output of the shaper.

The classifier shown in FIG. 7, generates a signal "P" or "O" based on a comparison of the input information with threshold values and consists of the first 13.1 and second 13.2 comparators, the first 13.3 and second 13.4 keys. The information inputs of the comparators 13.1 and 13.2 are connected simultaneously to the information input of the classifier, and their threshold inputs are respectively connected to the inputs of the " _class " and " _class " of the classifier. The output ">" of the comparator 13.1 is connected to the information input of the key 13.3, and the output "<" of the comparator 13.2 is connected to the information input of the key 13.4. The control inputs of the keys are connected simultaneously to the clock input of the classifier, their outputs are respectively the outputs "P" and "O" of the classifier.

In FIG. 8 is a schematic diagram of a search strategy register that generates an interval or point value of classification thresholds depending on whether the number of the search interval is limiting or not. It consists of registers 14.1, 14.2, comparator 14.3, subtractors 14.4 and 14.6, a divider into two 14.5, keys 14.7, 14.8, 14.9, OR circuits 14.10, 14.11. The information input of the comparator is connected to the input "N _current ", and its threshold input is connected to the input "N _max " of the search strategy register. The information inputs of the registers 14.1 and 14.2 are connected respectively to the inputs "Pv" and "Mon" of the search strategy register. The output of the register 14.1 is connected simultaneously with the inputs of the reduced subtractors 14.4 and 14.6 and the information input of the key 14.7. The output of the register 14.2 is connected simultaneously with the input of the subtracted subtractor 14.4 and the information input of the key 14.9. The output of the subtractor 14.4 is connected to a divider by two, the output of which is connected to the input of the subtracted subtractor 14.6. The output of the subtractor 14.6 is connected to the information input of the key 14.8, the control input of which is connected to the output ">" of the comparator. The output of the comparator "<" is connected simultaneously with the control inputs of the keys 14.7 and 14.9, the outputs of which are connected to the first inputs of the OR circuits 14.10 and 14.11, respectively. The second inputs of the OR circuits 14.10 and 14.11 are combined and connected to the output of the key 14.8, and their outputs are respectively the outputs of the “ _Cl key" and P _cl "of the search strategy register. The inputs of the initial installation of both registers are connected simultaneously to the" Reset "input of the search strategy register .

 The threshold signal change block (Fig. 9) is designed to change the threshold signal values depending on the time of day and consists of a decoder 17.1, encoder 17.2, register 17.3, adder 17.4 and subtractor 17.5. The input of the block "Time" is connected to the input of the decoder, the output of which is connected to the input of the encoder. The output of the encoder is connected simultaneously to the input of the first term of the adder and the subtracted subtractor. The information and clock inputs of the register are connected respectively to the input "Threshold" and "Start" of the block, and its output is connected simultaneously to the input of the second term of the adder and the reduced subtractor. The outputs of the adder and subtractor are respectively outputs "Pv" and "Mon" block.

 Blocks and devices not disclosed in this description can be implemented by methods (circuits) known from the literature, the possible construction options of which are given below.

Дешифраторы: 1.1, 2.1, 3.1, 17.1. Дешифратор имеет n входов и N выходов и выполняет следующую функцию: каждому входному слову (n разрядному входу), т. е. комбинации единиц и нулей на входе, соответствует сигнал "1" на одном определенном выходе; обычно сигнал "1" появляется на той выходной шине, номер которой в двоичной форме совпадает с входным n разрядным кодом. Структура дешифратора на 3 входа и 2³=8 выходов показана в (Гольденберг Л.М. Импульсные и цифровые устройства. Учебник для ВУЗов. М.: Связь 1973, с. 496) на рис. 10.12. Аналогичным образом строится дешифратор на n входов и 2ⁿ=N выходов.Counters: 4, 1.4, 1.5, 2.2, 3.2. The totalizer modulo k = 2 ^{m is} formed by connecting m triggers. As an example in fig. 10.4a (Goldenberg L. M. Pulse and digital devices. A textbook for high schools. M .: Communication, 1973, p. 496) a circuit is shown consisting of four cascade-connected triggers. Table 10.4 of the same textbook shows the state of the triggers depending on the number of input pulses. If at the input of an m-bit counter, consisting of m series-connected triggers, n pulses appeared during a certain time interval, moreover:
N = n2 ^m + a _m 2 ^m-1 + a _m-1 2 ^m-2 + ... + a ₁ 2 ⁰ ,
Where
a ₁ (i = 1,2,3,4 ... m) =

Decoders: 1.1, 2.1, 3.1, 17.1. The decoder has n inputs and N outputs and performs the following function: each input word (n bit input), that is, a combination of ones and zeros at the input, corresponds to a signal “1” at one specific output; usually the signal "1" appears on the output bus whose number in binary form matches the input n bit code. The structure of the decoder for 3 inputs and 2 ³ = 8 outputs is shown in (Goldenberg L.M. Pulse and digital devices. Textbook for universities. M .: Communication 1973, p. 496) in Fig. 10.12. In the same way, a decoder for n inputs and 2 ⁿ = N outputs is constructed.

,
где

- наименьшее целое, не меньшее чем X.Encryptors: 1.2, 1.3, 2.3. . .2.6, 17.2. The encoder for N inputs is constructed similarly to that shown in (Sikarev A.A., Lebedev O.N. Microelectronic devices for generating and processing complex signals. M: Radio and communication, 1983, p. 216) in Fig. 43, p. 49 encoder for 10 inputs and 4 outputs using the table. 15 p. 48. Moreover, the number of outputs n of the encoder is:

,
Where

is the smallest integer not less than X.

.Delay Elements: 3.3 ... 3.5. They are delay lines (LZ). The signal at the output of the delay line is reproduced with a certain delay for a certain period of time t ₃ . A LZ can be constructed by connecting one-input OR circuits in series, each of which has t _3i for a certain basis (a series of microcircuits). Then

.

 Another possible implementation is shown in (Goldenberg L.M. Pulse and digital devices. Textbook for high schools. M .: Communication., 1973, p. 496) in Fig. 1.27.

 Comparators: 2.10. . .2.11, 13.1, 13.2, 14.3. The comparator performs the operation of comparing two n bit numbers A and B and generates a signal “1” at one of the three outputs (A <B, A> B, A = B); the number of comparator inputs is 2n. When comparing two-digit numbers, the comparator is based on the table. 2.10 on p. 51 (O. Lebedev, A. M. Sidorov. Pulse and digital devices. Digital nodes and their design on microcircuits. L .: VAS, 1980, p.128) and is implemented in Fig. 2.33 (p. 52). Since comparison schemes have the property of scalability, the comparator for comparing two n-bit numbers is constructed by analogy with Table. 2.11, fig. 2.35, p. 53-54, to the desired value of n.

 Registers 14.1, 14.2, 17.3 and memory blocks 10, 11 are registers of parallel action. The construction of such registers from n inputs and n outputs is shown in (Shlyapobersky V.I. Fundamentals of Discrete Message Transmission. M.: Communication, 1973, p. 480) in Fig. 3.1, p. 106. The indicated registers are also used as memory blocks storing one element (operand) during one analysis interval.

 The adder 17.4 and the totalizing counters 8.9 are arithmetic adders. The adder (parallel) is constructed similarly to Fig. 14.17, p.377 (Fundamentals of pulsed and digital technology. Textbook for high schools. M .: Soviet radio, 1975, p. 440), where the half-adder is shown in Fig. 14.13, and the full adder - Fig. 14.14.

 Subtractors: 2.7. ..2.9, 14.4, 14.6, 17.5. The subtractor is built on the basis of the adder, on one input of which a decremented signal is supplied, on the other - an addition to the unit of the deductible (the negation of the deductible - through the NOT circuit - is added bitwise modulo two with unity).

 Keys: 2.12 ... 2.14, 13.3, 13.4, 14.7, 14.8, 14.9. The key, in the general case, is built in the form of a multiplexer, the construction principle of which is described in (Lebedev, O.N., Sidorov, A.M., Pulse and Digital Devices. Digital Nodes and Their Design on Microcircuits. L .: VAS, 1980, p. 128) p. 54. The implementation of a multiplexer for 8 channels controlled by a 3-element code is shown in Fig. 2.36, p. 55 (built on the basis of table 2.12, p. 54). With a single-bit control input, the multiplexer degenerates into the simplest key, which is most often implemented by n-input circuits I.

 Division devices: 12, 2.16, 2.17, 6.2. The division device for two n-bit binary numbers is based on the division algorithm without restoring the remainder described in (Bocharov K.P., Nemshilov N.N., Petrov E.I., Sulin L.I. Computational complexes of automated control systems. L .: YOU, 1984, p. 368), pp. 88-90, fig. 3.24 (a). The scheme of the division device is presented on p. 89, fig. 3.24 (b). The result of division is an n-bit binary number. In the case when the bit depth of the numbers dividing the input device is different, for n we take a larger bit depth. A number with a lower bit capacity is represented as n-bit, adding zeros to the upper digits.

 A device for dividing by two for binary numbers is implemented by reading the operand from the output of the previous device without a high order, which is the equivalent of dividing it by two.

 Multiplier: 6.1. The multiplier of two n-bit binary numbers can be implemented on the basis of one of the four given in (Bocharov K.P., Nemshilov N.N., Petrov E.I., Sulin L.I. Computational complexes of automated control systems. L.: VAS , 1984, p. 386) on p. 68-69, fig. 3.19, the basic multiplication schemes, which are described on p. 65-71. The result of the multiplication is a 2n-bit binary number. In the case when the bit capacity of the multiplied numbers is different, for n we take a large bit capacity. A number with a lower bit capacity is represented as n-bit, adding zeros to the upper digits.

 The reset signal generator is a circuit for combining the “P” and “O” signals, as well as their amplification and matching with subsequent blocks. It can be made in the form of a two-input OR circuit with increased load capacity.

 The information retrieval device operates as follows.

 To minimize the sample size, a consistent decision selection procedure is used. At the same time, the sample size is not fixed, but limited in the process, depending on the result of previous observations. The decision-making process becomes multi-step. First, one value of a random variable is observed, and according to a predetermined rule, either the observation is terminated and a decision is made, or the observation continues. If the rule prescribes a rejection of the decision, then evaluate the next sample. The test ends on the same sample, on the basis of which the observation in accordance with the stopping rule is stopped and a decision is made (VV Popovsky. Mathematical modeling of complex systems. L., VAS, 1990).

 When using a sequential rule, the stopping time of the observation process is random, therefore, the sample size at which the final decision is made is random. In a particular case, the sample size may turn out to be excessively large and the sequential procedure is longer than inconsistent.

To eliminate this drawback, the proposed device uses a truncated sequential procedure in which the maximum sample size is limited to a certain number N _max . With this procedure, for all N <N _max , the interval values of thresholds with which the likelihood ratio is compared are established, as for the un-truncated rule. If the size of the analyzed sample reaches N _max , then the point values of the thresholds are set at which a decision is made in any case, and the observation cycle is repeated. In turn, the threshold values change depending on the time of day, since this factor determines the quantitative indicators of the input traffic. Varying with thresholds reduces the time it takes to make a decision while meeting specified requirements for the probability of false alarm (α) and signal skipping (β).

As noted above, the state of the situation is estimated by the intensity of the input traffic on the N + 1 observation interval, which is determined through the intensity of the arrival of the SSC combinations. The degree of intensity is an informational array, divided into two classes “P” and “O”, corresponding to the estimates “Present” and “Absent”. The description of the class of states “P” is F _p (N) - the empirical integral distribution function of the sample values of the spread coefficient K _j prior to the estimates of “P” _{N + 1} . The description of the class "0" is the function F ₀ (N), built on the values of K _j previous estimates "0" _{N + 1} .

The data for statistical conclusions are random values of the coefficient of scatter K _j measured at some time intervals t _N , where 1 <N <N _max (E. Mushik, P. Muller. Methods for making technical decisions. M: Mir, 1990).

и величина L(N) сравнивается с нижним и верхним порогами классификации:

где
α и β - заданные вероятности ложной тревоги и пропуска сигнала соответственно.The task of sample analysis is reduced to a truncated sequential decision-making procedure in which, after each observed time interval t _N , the likelihood ratio is calculated:

and the value of L (N) is compared with the lower and upper thresholds of classification:

Where
α and β are the given probabilities of false alarm and signal skipping, respectively.

 The input information stream enters the information inputs of the shaper 1 of the signals of the current rating and the discriminator of 2 zones of the evaluation values.

 In shaper 1 (Fig. 2), the signal of the current time of day from the “Time” input of the shaper is sent in the form of a time code to the input of decoder 1.1 and then to encoders 1.2 and 1.3, which generate signals corresponding to the upper and lower boundaries of the search range. These signals change the conversion factors of the counters 1.4 and 1.5 in accordance with the law of change in the intensity of the supply of SPS from the time of day. When the deviation of the number of SPS from the average value to the upper or lower side is greater than the threshold at the output of the corresponding counter (1.4 or 1.5), the signal "P" is generated , in other cases, the signal "O" is generated. At the beginning of each analysis interval, the counters are initially set up with a signal from the shaper synchronization input.

In the discriminator of the zones of the evaluation values (Fig. 3), the SSC input stream is counted by a 2.2 counter for the time interval determined by the period of the clocked sequence. The obtained value of the number of KNS - S _{KNS is} compared on comparators 2.10 and 2.11 with the upper and lower threshold values - S _PV and S _PN , which determine the range of values corresponding to the conditions of the situation "P" and "O": the state region "O" is between the upper and lower thresholds, and the “P” region is below the lower threshold and above the upper threshold. S _PV is formed by the decoder and encoder 2.3, and S _PN - by the decoder and encoder 2.4. S _{KNS is} compared on comparator 2.10 with S _PV , and on comparator 2.11 - with S _MON . The output ">" of the comparator 2.10 controls the key 2.12, and the output "<" of the comparator 2.11 controls the key 2.14. 2.12 An information key is input difference values S _CND - S _MF from subtractor 2.7, and the information input key 2.12 - _Mo difference S - S _CND, which defines the environment conditions "P". The key 2.13 is controlled simultaneously by two inputs (logical function AND): from the output "<" of the comparator 2.10 and from the output ">" of the comparator 2.11. The information input of this key receives the difference S _PV - S _KNS , which determines the area of the state of the situation "O". The encoders 2.5 and 2.6, together with the decoder 2.1, form the width of the estimation zone for the areas “P” and “O”, respectively, expressed by the number of KNS - S _KNS P and S _KNS O. These values are a divisor in division devices 2.17 and 2.16, respectively, divisible by are the differences, respectively, S _KNS - S _PV or S _PN - S _KNS and S _PV - S _KNS . After the division operation, the zone number corresponding to a more accurate assessment of the state of the situation, in comparison with the estimate obtained in the signal conditioner of the current assessment, appears at the output of the discriminator.

В суммирующих счетчиках 8 и 9 производится сложение значений приращений F_п(N) и F_о(N) с соответствующими значениями эмпирической интегральной функции распределения, вычисленной за N-1 временной интервал F_п(N-1) и F_о(N-1), которые поступают с выходов блоков памяти 10 и 11:
F_п(N) = F_п(N-1) + F_п(N);
F_о(N) = F_о(N-1) + F_о(N).The counter 4 time intervals (Fig. 1) calculates the number of observed time intervals and provides a combination of the number of time intervals on the register 14 of the search strategy. The switch 5, in accordance with the control signal received from the driver 1, connects the signal about the status zone number "P" or "O", respectively, to the input of the search variable driver 6 or 7, where based on the signal about the zone number K _j (1 <j <m), the largest zone number K _m and the maximum number of observations N _max , the increments F _p (N) or F _о (N) of the empirical integral probability distribution functions of the deviated and normal traffic state are constructed on the Nth observation interval:

In the summing counters 8 and 9, the increment values F _p (N) and F _о (N) are added together with the corresponding values of the empirical integral distribution function calculated over the N-1 time interval F _p (N-1) and F _о (N-1 ) that come from the outputs of memory blocks 10 and 11:
F _p (N) = F _p (N-1) + F _p (N);
F _o (N) = F _o (N-1) + F _o (N).

и выдачу отношения правдоподобия на вход классификатора 13.The values of F _p (N) and F _about (N) are fed to the inputs of the division unit 12 and are recorded in the first 10 and second 11 memory blocks. The division unit 12 performs the operation of arithmetic division

and issuing a likelihood ratio to the input of the classifier 13.

When the value of the input signal of the classifier (Fig. 7) is less than the lower threshold (P _kln ) of the comparator 13.2, a high potential is formed at its output “<”, opening the key 13.4, which corresponds to the state of the situation “O”. When the value of the input operand of the classifier is greater than the upper threshold (P _cl in) of the comparator 13.1, a high potential is formed at its output ">", which opens the key 13.3, which corresponds to the state of the situation "P". Intermediate values of the operand at the input of the classifier do not lead to the development of a solution as long as the search strategy remains two-threshold. When the search procedure is truncated (when the limit value of the search interval number is reached), the thresholds “merge”, which in any case leads to a decision on the state of the situation.

Change the search strategy carried out by the register 14 (Fig. 8), as follows. The thresholds “Pv” and “Mon” from the input of the search strategy register are respectively sent to the inputs of the registers 14.1 and 14.2, which then, when the value of the number of the current search interval is less _{than the} maximum allowable (N _current <N _max ), are fed to the corresponding outputs of the search strategy register through the public keys 14.7 and 14.9, as well as OR circuits 14.10 and 14.11 as the values of the classification thresholds “P _cl in” and “P _cl n”. This state corresponds to the interval value of the search threshold, which is necessary for the implementation of the search procedure according to the Wald criterion. With N _current ≥ N _max , the low potential closes the keys 14.7 and 14.8 at the output of the <<comparator, and the high open key 14.8 closes at the output ≥. In this case, the threshold difference value obtained at the output of the subtractor 14.4 is divided by a division device 14.5 into two and, after subtracting it from the value of the upper threshold in the subtractor 14.6, it becomes equal to the average value between the upper and lower thresholds. This value through the public key 14.8 is supplied simultaneously to both outputs of the search strategy register through the OR circuits 14.10 and 14.11, which is equivalent to the formation of the point value of the search threshold. Initialization of the register of the search strategy is carried out by setting all the registers to the initial state with the "Reset" signal coming from its input of the same name.

 The adaptation of the search thresholds to the time of day is carried out in block 17 (Fig. 9). The current time code arriving at its input from timer 18, from the “Time” input of the block, is sent to the decoder and then to the encoder, which form a signal that displays the law of change in the intensity of the input traffic necessary to control the dependence of the threshold values on the time of day. With the arrival of the "Start" signal, the threshold value is recorded in the register 17.3 and simultaneously appears on its output as the second operands of the adder 17.4 and subtractor 17.5. The signal from the decoder, proportional to the deviation of the thresholds, is added to the average threshold value in the adder 17.4 and subtracted from it in the subtractor 17.5. As a result, the upper and lower threshold values are formed at the block outputs, depending on the time of day. The average threshold value is a statistical a priori value and is set by writing to the register the corresponding value from the input of the Threshold block.

 The signal from the output of the classifier 13 is fed to the input of the display unit 16 and the shaper of the reset signals 15, from the output of which the signal "Reset" is sent to reset the counter 4, the first 10 and second 11 memory blocks, as well as register 14 to reset them.

 All blocks, devices and elements that process the information signal, as well as the lines connecting them, must have a bit width corresponding to the bit width of the input operands and the accuracy of their transformations.

 Evaluation of improving the efficiency of information retrieval in the proposed device was carried out as follows.

для минимизации Т_тр. Указанное характеризует физический смысл формул (2) и (9).Note that for K _mp → min it is advisable μ → μ _max (provided

to minimize T _Tr . The above characterizes the physical meaning of formulas (2) and (9).

 Dichotomous method (used in the prototype).

1. To _tr. = r • K _about. where r is the density coefficient (r ≥ 1).

где Т_тр.дих. _→ требуемое время поиска искомых блоков.S _tr = K _Tr. • μ; S = K _vol. • μ _ → S _tr. = r • K _vol. • μ _tr.
Since in order to exclude skipping or false alarm, the condition must be met: μ _tr. ≤ μ / 2, then:

where T _tr. _ → the required time to search for the desired blocks.

Проведя упрощения и взяв антилогарифм в выражении (5), получаем (М.Я. Выгодский. Справочник по элементарной математике. М.: Наука, 1964):

Полагаем S = 10⁶.In the general case, the ratio T _dich. and T _tr. estimated:

After simplifying and taking the antilogarithm in expression (5), we obtain (M.Ya. Vygodsky. Handbook of elementary mathematics. M: Nauka, 1964):

We set S = 10 ⁶ .

Let us estimate the ratio T _dich. and T _tr. at K _Tr. = (0.15 - 0.25).

Проведя упрощения и взяв антилогарифм в выражении (6), получим:
ΔT_дих.max= T_дих./T_тр.дих.= 1,0528.
Т.е.: 1,0528 < ΔT_дих.max< 1,0955
II. В нашем случае:

Последовательный метод, реализованный в предлагаемом устройстве, оценивается следующим образом.

Having simplified and taking the antilogarithm in the expression (6), we obtain:
ΔT _dich.max = T _dich. / T _tr. = 1.0528.
That is: 1.0528 <ΔT _dich.max <1,0955
II. In our case:

The sequential method implemented in the proposed device is evaluated as follows.

III. К_тр. = (0,15 - 0,25) • К_об..

III. To _tr. = (0.15 - 0.25) • To _about. .

Проведем оценку соотношения Т_посл. и Т_{тр.посл.} аналогично пункту (I).

Let us evaluate the ratio of T _last. and T _{tr. after} similar to paragraph (I).

Т.е.: 2,00 < ΔT_посл.max< 3,33
IV. Пусть К_тр. = (0,80 - 0,90) • К_об.
Проведем оценку соотношения Т_посл. и Т_{тр.посл.} аналогично пункту (II).

I.e.: 2.00 <ΔT _last.max <3.33
IV. Let K _tr. = (0.80 - 0.90) • To _about.
Let us evaluate the ratio of T _last. and T _{tr. after} similar to paragraph (II).

Т.е.: 0,556 < ΔT_посл.min< 0,625
Сравним попарно полученные результаты.

I.e.: 0.556 <ΔT _{last min} <0.625
Compare the results obtained in pairs.

Иллюстрации приведены на фиг. 10.For K _tr. = (0.15 = 0.25) • To _about.

The illustrations are shown in FIG. ten.

Иллюстрации приведены на фиг. 11,
где:
Graph D - гистограмма для дихотомического метода;
Graph P - гистограмма для последовательного метода.For K _tr. = (0.8 - 0.9) • To _about.

The illustrations are shown in FIG. eleven,
Where:
Graph D - a histogram for the dichotomous method;
Graph P is a histogram for a sequential method.

Thus, the results allow us to conclude that at K _Tr. _ → K _about. it is advisable to use the sequential method of searching for information as an alternative to the dichotomous one, since the time gain of the first method compared to the second can be up to 35 - 40%. The proposed device, in which a set of new blocks and a sequential procedure with restrictions by the Wald criterion are used to search for information in the array and evaluate it, ensures the achievement of the goal.

Claims (5)

1. An information retrieval device comprising a pulse distributor, a first search variable shaper summing a counter and a memory unit, as well as a search strategy register, characterized in that a second search variable shaper summing a counter and a memory block, a current evaluation signal generator, discriminator are additionally introduced zones of evaluation values, a counter of time intervals, a switch, a division unit, a classifier, a block for changing threshold signals, a timer for the current day, an indication unit, and a signal shaper reset, the information inputs of the current estimator and the discriminator of the valuation values zones are combined and are the information input of the device, the first output of the pulse distributor is connected simultaneously to the synchronization inputs of the current estimator and the discriminator of the valuation values of the zones, as well as to the clock input of the time interval counter, and the second , the third and fourth outputs of the pulse distributor are connected respectively to the clock inputs of the switch, the first and second memory blocks and class fixture, the output of the current day’s timer is connected simultaneously to the “Time” inputs of the pulse distributor, the current estimator, the discriminator of the evaluation value zones and the threshold signal change unit, the outputs of the search threshold values of which are “Pv” and “Mon” are connected to the same inputs of the search strategy register , the outputs of the upper and lower threshold values of the classification is "n _cl c" and "n _Cl n" are connected to respective inputs of the classifier, which outputs "O" and "O" are connected simultaneously to respective inputs blo s display and the driver reset signal, the output of which is connected simultaneously to inputs "Reset" of the first and second memory blocks, the counter slots and registers the search strategy, input "N _teksch" is connected to output timeslots of the counter, the output of the first generator variable search connected to the first information input of the first totalizing counter, the second information input of which is connected to the output of the first memory block, and the output of the first totalizing counter is connected simultaneously with the information the input of the first memory unit and the first information input of the division unit, the output of which is connected to the information input of the classifier, the output of the second totalizing counter is connected simultaneously to the second information input of the division unit and the information input of the second memory unit, the output of which is connected to the second information input of the second totalizing counter, the first the information input of which is connected to the output of the second driver of the search variable, the information input of which is connected to the output "O" of the switch , the output "P" of which is connected to the information input of the first driver of the search variable, the inputs "N _max " of the first and second drivers of the search variable, as well as the search strategy register are connected simultaneously to the device input of the same name, and the inputs "Zone1" and "Zone2" of the device are the “Zone” inputs, respectively, of the first and second variable search formers, the control input of the switch is connected to the output of the current evaluator, and the inputs of the “P” and “O” are connected to the corresponding discriminator outputs zones estimation values, inputs "threshold" and "Start" of the device connected to the homonymous input of the threshold signal change unit.  2. The device according to claim 1, characterized in that the current evaluator signal shaper consists of a decoder, first and second count coefficient encoders, first and second counters, NOT and OR elements, the “Time” input of the shaper is the decoder input, the output of which is connected simultaneously with the inputs of the first and second encoders, the outputs of which are connected to the inputs of setting the account coefficients, respectively, of the first and second counters, the counting inputs of which are connected simultaneously to the information input, and the clock inputs to the sync input tions generator, the first counter output is connected to the first input of the OR gate, the second input of which through the element is coupled to the output of the second counter, the output element is the output of OR.  3. The device according to claim 1, characterized in that the discriminator of the zones of the evaluation values consists of a decoder, counter, first, second, third and fourth encoders, first, second and third subtracters, first and second comparators, first, second and third keys, OR circuits of the first and second division devices, the discriminator's “Time” input is an decoder input, the output of which is connected simultaneously to the inputs of all encoders, the information input and the discriminator synchronization input are information and tact the input inputs of the counter, the output of which is connected simultaneously to the inputs of the decreasing first subtractor, as well as the subtractable second and third subtractors, and to the information inputs of both comparators, the threshold input of the first comparator, the input of the subtractable first and the input of the decreasing second subtractors are combined and connected to the output of the first encoder, the threshold the input of the second comparator and the input of the reduced third subtractor are combined and connected to the output of the second encoder, the outputs of the third and fourth encoders are connected to the input and a dividend, respectively, of the first and second division devices, the divider inputs of which are connected respectively to the output of the second key and the output of the OR circuit, the outputs of the first, second, and third subtractors are connected to the information inputs of the first, second, and third keys, the outputs of the first and third keys are connected respectively to the first and second inputs of the OR circuit, the outputs "<" of the first and second comparators are connected respectively to the first control input of the second and control input of the third key, the outputs ">" of the first first and second comparators respectively connected to a control input of the first switch and a second control input of the second switch, the outputs of the first and second division units are respectively outputs "O" and "O" of the discriminator. . 4. The apparatus according to claim 1, characterized in that the classifier consists of first and second comparators and the first and second key information inputs of the first and second comparators are connected simultaneously to the data input of the classifier, and their threshold inputs - respectively to the inputs of 'n _Cl in "and" n _Cl n "classifier outlet">"of the first comparator is connected to the data input of the first switch, and the output"<"second comparator - a data input of the second switch, the control inputs of the keys simultaneously connected to the clock input of the class of the classifier, the outputs of the first and second keys are respectively the outputs "P" and "O" of the classifier. 5. The device according to claim 1, characterized in that the search strategy register consists of the first and second registers, the first and second subtracters, the device of division into two, the comparator, the first, second and third keys, the first and second OR circuits, the information input of the comparator connected to the input "N _text ", and the threshold input to the input "N _max " of the search strategy register, the information inputs of the first and second registers are connected respectively to the inputs "P _in " and "P _n " of the search strategy register, the output of the first register is connected simultaneously with inputs of the first and second subtractors and the information input of the first key, the output of the second register is connected simultaneously with the input of the subtracted first subtractor and the information input of the third key, the output of the first subtractor is connected to the input of the divider by two, the output of which is connected to the input of the subtracted second subtractor, the output of which is connected with the information input of the second key, the control input of which is connected to the output "≥" of the comparator, the output "<" of which is connected simultaneously with the control inputs of the first and third of the keys whose outputs are connected to the first inputs of the first and second OR circuits, respectively, the second inputs of which are combined and connected to the output of the second key, the outputs of the first and second OR circuits are outputs of the “ _Cl key" and " _Cl key" of the search strategy register , and the inputs of the initial installation of both registers are connected simultaneously to the input "Reset" of the search strategy register.

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