SU555404A1 - Device for orthogonal digital signal transform by Walsh Hadamard - Google Patents

Description

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delays. After the first four sums have arrived at the output of the first conversion stage, the switches are set to the previous state and the differences recorded in the main unit, through the auxiliary unit, are transferred to the output of the conversion channel. Further, the operation of the first channel is repeated. The second and third channels work in the same way as the first, only the switches are switched twice and four times as often respectively. At the output of the third conversion channel, Walsch conversion coefficients are sequentially obtained from a sequence composed of the first eight values of the input signal, then from the next eight, and so on. This device is characterized by complexity of the design.

The closest to the technical essence of the invention is a device containing a control unit and in each channel two delay units and an arithmetic unit whose control input is connected to the corresponding output of the control unit, the device input is connected to the input of the first delay unit and to the first input of the arithmetic unit of the first channel 2. The unit transformation channel at the first conversion stage contains the first delay block, in which the discrete CHrfia / ra delay is performed and the time is equal to the following clock cycle kretnogo signal. The arithmetic unit is designed to receive the sum and the output signals from the first delay unit. The second delay unit implemented a delay of 10 times the signal from the output of the arithmetic unit for a time equal to the delay time in the first delay unit and the delay of numbers twice as large as in the first delay unit. Sweep Whitefish it yCTp.n iciBe is issued in such a way that the sum signal from the arithmetic unit and the difference signal from the second delay unit is / sec / gats with a time interval equal to the delay time n delay units. At each subsequent stage of the conversion, the unit channel contains delay blocks at the time c; c) more than at the previous stage, and storage of numbers twice as large as at the previous stage is given. The number of transformation steps depends on the length, the discrete signal being processed, or on the order of the transform 1 and.

. Delay blocks are 1 on shift registers. In order to delay multiple bits and a split, several shift registers must be connected in parallel. In each unit transformation channel, the second delay unit serving the differential signal delay w / w must have the number of regasters connected in parallel to ia oshp (larger than the first unit, since oi must delay the numbers of ow. .Jalosta; o.xciro) ispi1 is its complexity and apppprat | -: 1 ;. cumbersome.

The purpose of the invention is to simplify the device. This is achieved by the fact that in the device the output of the arithmetic unit of each channel, except the last one, is connected to the input of the first delay unit and the first input of the arithmetic unit of the subsequent channel, the output of the first delay unit in each channel is connected to the second input of the arithmetic unit and through the second delay unit to the third input of the arithmetic unit. The output of the arithmetic unit of the last channel is connected to the output of the device.

FIG. 1 is a diagram of the device; in fig. 2 is a graph of the sequence of calculations.

The serially connected single conversion channels contain two delay units li-l3.2i-2z and an arithmetic unit 3i-3. The control inputs of the arithmetic units are connected to the outputs of the control unit 4; the input of the device is indicated by the number 5, and the output by the number 6. Delay blocks in the first channel of a single

the transformations delay the input discrete signal by one clock each. The delay blocks in each subsequent channel delay twice as large as in the previous channel.

Consider the operation of the device on the example of a device for orthogonal transformation of the order of 8 (see Fig. 2). In this case, the delay blocks of the first channel have one bit of the shift register, the second channel two, and the third channel four. With the frequency of the clock pulses, the values of the discrete signal are successively connected to the input of the first channel. The arithmetic unit outputs one by one the summation of the signal outputs from the output and input of the first delay unit and the subtraction of the signal values from the output and input of the second delay unit.

Values of the sum and difference come in

the second conversion channel where produced

similar calculation) w, but the delays of each

block and the sum of the summable and calculated

The number doubles.

The delay blocks in each channel have the same number of shift registers connected to each other, since the second delay block, in contrast to the known device, delays the same patterns as the first delay block. This leads to simplicity of the device.

In addition, the implementation of arithmetic units is simplified, since summation and subtraction of numbers are performed alternately.

Claims (2)

1. US Patent N 3742201, M.C. G 06 F 7/38, 15/34, 1973 2. US Patent No. 3792355, M.C. 2 H04 J 3/18, 1974. (prototype). Ф14г.1 subtraction Bedrock Fig 2