SU538495A1 - Multichannel pulse counter - Google Patents

Description

one

The invention relates to computing and can be used in specialized computing devices.

Multichannel counters are known, in which each digit contains counters i.

However, counters are known to be complex.

Multichannel pulse counters are known, which carry out the counting of pulses with time division channels and contain K registers for storing the counting results by K channels, a channel switch and an arithmetic unit for summing the unit. N + 1 register and N combination blocks are used as an arithmetic unit one of the registers is connected to the input of the next through the combinational unit 2.

However, this known device is also complex.

The aim of the invention is to simplify the multi-channel pulse counter.

For this, a multichannel pulse counter containing N registers, a channel switch and (N - i) -and register, with the outputs of the channel switch connected to the inputs of each register, except for (N + 1) -th, inputs (N + 1) -th the register is connected to the outputs of all N registers, and the inputs of all N registers are connected to the outputs of the (N + 1) -th register, and the Lth output of the (N + 1) -gc register is connected to the (I + 1) -th inputs of all N registers where t. l, 2, ..., n.

The drawing shows a structural electrical circuit of the meter.

Each bit of the multi-channel pulse counter contains registers 1 and 2, the number of which is equal to N, i.e. number of channels. In addition, the counter contains N + 1 register 3 and switch 4, the first input 5

Register 3 is connected to the first outputs 6 of all IN registers 1 and 2, and their inputs 7 are connected to Gp with output 8 of register 3. The second inputs 9 of registers 1 and 2 are connected to the first output 10 of register 3, the second outputs 11 of registers 1 and 2 connected to the second input 12 of register 3, similarly m-th input 13 of register 3 is connected to m-output 14 of registers 1 and 2. Input 15 of register 1 is connected to the first output 16 of switch 4, and input 17 of register 2 is connected to | n- output 18 of the switch 4. Inputs 19 of registers 1 and 2 are connected to the input of a multichannel pulse counter.

The proposed device operates as follows. The input pulse arrives at inputs 19 of registers 1 and 2. Suppose, for example, the result of summing up a first channel in this bit is 0. Then, when an input pulse arrives and a signal is output at output 16 of switch 4, a pulse from output 6 of register 1 is fed to input 5 of register 3 the signal from output 10 is fed to the input 9 of register 1 also when forming the signal at output 16 of switch 4.

Thus, the result of the counting in this bit of the first channel becomes 1. After the arrival of the m-th input pulse, the pulse outputted from output 14 of register 1 is fed to input 13 of register 3 and simultaneously to the input of the next bit. This is how the end-to-end transfer is organized. After that, the pulse from output 8 of register 3 is fed to input 7 of register 1, i.e. the last is recorded wcno o.

Simplification of the multichannel pulse counter is achieved by using a register instead of an arithmetic unit, the latter, like the channel switch, may be identical to the other N registers.

Claims (2)

1. USSR author's certificate No. 331383, MKI GO6 M 3/08, 1972 2. USSR author's certificate No. 310402, MKI H 03 to 23/00 1972 (prototype).