SU375636A1 - LIBRARY - Google Patents

Description

one

The invention relates to computing and can be used in an aggregate system of computer aids (ASVT).

As part of the ACBT, multichannel group devices are known for the aialo-digital conversion of electrical signals. In ASBT, sensors with an analog output are connected to the inputs of these devices, and a memory device or an ASBT processor is connected to the output.

When using: known devices for group analog-to-digital conversion at a high conversion frequency in a memory device to which an AV-digital conversion device is connected, a very significant amount of numerical information is accumulated in a short time, the processing of which on an ASBT processor requires considerable time

The purpose of the invention is to enhance the functionality of analog-digital devices for information conversion.

In the proposed device, this is achieved by summing the incoming numbers for some time, as a result of which the number of numbers transferred to the processor for processing is reduced by several times, which significantly reduces the processing time of information in the processor and allows for a wider use of these devices. FIG. 1 shows a block diagram of a part.

the proposed device for one channel, the exits to the other channels are indicated by arrows; in fig. 2 is a block diagram of the entire device. Summation of numbers in each channel

The proposed device (Fig. 1) is carried out in a summator Y and a counter 2. Information from the output of the analog-digital preamplifier 3 goes to adder 1, the overflow units from the adder go to

counter 2. If this counter overflows, the overflow unit switches the potential symmetric trigger 4, to: the output of which a high voltage level appears, which takes the key 5 and the corresponding keys of the other channels. The information accumulated in the adder 2 and the counter 1, through the key 6, is rewritten into the shift register 7 according to the signal generated when the flip-flop 4. tilts. This signal

delayed by the delay line 8 and fed to the imaging unit 9 by him; pulses, which produces the census resolution signal for the key 6. Rewritten to the shift register 7, the iforMaty can be rewritten into the memory or

an ASBT processor, by a signal / arriving via bus 10 from an ASVT processor to a ring counter 11, with which it is produced sequentially; rewrite the contents of all shift registers in the memory or processor. The signal .c output.- (p + O-th ring counter 12 is recorded in the memory or the processor of the contents of the counter 13, which contains information on the number of summation acts.

The device can operate in three modes:

totaling one of the counters 2 to overflow;

the summation over a certain fixed time interval, which is set by the processor software tires 14 and .15 (the tire 14, the impulse to start the summing comes, the tire 15 ends the summation);

summation to a given number of acts of summation.

In the latter mode, the number P p – t is transferred from the processor to the counter 17, where t is the counter recalculation module, / is the specified number of summation acts. With each act of summation, the contents of the counter / 7 are incremented by one. After viewing the specified number of a-kts of summation, an overflow of counter 17 occurs, the overflow unit switches trigger 4 and the summation stops.

If the number of committed summation acts turns out to be a multiple of 2, where q is any number, then from the number stored in the shift register, an arithmetic average of the summed numbers is generated. In this case, the contents of the counter 13 through the keys 18, the decoder 19, the circuit on the rectifying diodes and the form factor. The pulse driver 20 is rewritten into the shift register 21. The circuit on the output diodes

when a signal appears on a bus of any bit, 01 ensures that the unit is written to this bit of the shift register and to all the lower bits. The signal delayed by the delay line 22 opens the keys 23 connecting the shift input of the register 21 with the pulse generator 24, shifting the contents of the shift register 2 to the right until the register is cleared. The pulses from the output of the shift register 20, formed by the shaper 25, shift the contents of register 7 (all channels) to the right by the necessary number of bits, after which the contents of these registers become equal to the arithmetic mean of the summed numbers.

The device (Fig. 2) contains one control unit of the CU and / g blocks of the BS summation, where n is the number of channels.

Subject invention

Claims (2)

1. A device for transforming information containing a control unit and in each channel an analog-to-digital converter connected to a key, characterized in that, in order to broaden the scope of application, a summation unit connected to the outputs of the analog-digital is entered into it in each channel converter and control unit. 2. The device according to claim 1, characterized in that in the control unit, the output of the counter of the number of summations through the first key is connected to the decoder, the outputs of which are interconnected via diodes and connected through the pulse shaper to the shift register, the shift input of which is via the second connection key. with generator PULSES. About BK.I QSx.2 Memory, pr014sessor F1 / g. 2