SU822182A2 - Device for computing the difference between two n-digit numbers - Google Patents

Description

54) DEVICE FOR CALCULATING THE DIFFERENCE OF TWO N-BIT NUMBERS

one

The invention relates to automation and computing and can be used in information processing and control systems. According to the main auth. No. 739532, a device for calculating the difference of two-n-bit numbers, containing counters for decreasing and subtracting, a generator of pulses, triggers and elements, And the inputs of counters of registers of the subtracted are connected to the first output of the generator of pulses, an output.

The first (i 1, ..., p) counter-register of the deductible is connected to the single input of the i-oro trigger of the first group of triggers, the zero output of which is connected to the first input of the i-oro element I of the first group, the second input of which is connected to the second the output of the pulse generator, and the output with the input of the i-th counter register reduced, the output of which is connected to the single input of the i-th trigger of the second group of triggers, the single output of which is connected to the first input of the i-oro element II of the second group whose output is connected to the input ( -D) -th register counter zero, all the inputs of all the triggers, the second elements of the second group and the auxiliary input of the 5th counter of the register being reduced are connected to the third output of the pulse generator,

The disadvantage of this device is the ability to perform a subtraction operation only for the case when the deductible is greater than or equal to

0 deductible. The purpose of the invention is to expand the field of application of the device.

To achieve this goal, the device for calculating the difference

5 two n-bit numbers contain the third group of elements AND, the first input of the T-th element AND of the third group is connected to the output of the corresponding counter-register decreasing, and the second input - to the fourth-output of the pulse generator and the input of the corresponding counter-register decremented , the fifth output of the pulse generator is connected to the set of new inputs of counters-registers decreasing, and the control input - with the output of the first element And the second group.

The drawing shows a diagram of the device.

The device contains n counters-registers 1 subtracted, the inputs of which are connected to the first output of the generator 2 pulses. The i-oro output ((, ..., p) of the counter-register 1 is connected to the single input of the i-oro trigger 3 of the first group, the zero output of which is connected to the first input of the 1st element I 4 of the first group. The first output of the pulse generator 2 connected to the inputs of the counters of the subtracted 1. The second input of the i-th element And 4 is connected to the second output of the generator 2. And the output to the first input of the i-oro counter-register 5 is decremented. The output of the i-oro counter-register 5 is connected to the unit one the input of the first trigger b of the second group, the zero input of which is connected to the third output of the generator 2. A single The j-oro output (j-2, ..., n-) of trigger 6 is connected. It is connected to the first input of the j-th element And 7 of the second group, the output of which is connected to the second input (jl) -oro of the counter register 5. The zero output of the first trigger b of the second group is connected to the first input of the first element And 7 of the second group, the output of which is connected to the control input of the generator 2. The output of the i-th element And 8 of the third group is connected to the installation input i-oro of the counter-register 1 and the first input with the output of the i-th counter-register 5. The zero inputs of the triggers 3 are connected to the third output of the generator 2. The fourth in the generator 2 is connected to the second inputs of the And 8 elements and to the third inputs of the counter-registers 5. The second input of the nth counter-register 5 and the second inputs of the And 7 elements are connected to the third output of the generator 2, the fifth output of which is connected to the installation the inputs of the counters-registers 5. The number of states of the counters registers 1 and 5 is equal to the base of the selected number system.

The device works as follows.

In the initial state, in counters of registers 1, the value of the deductible is written bitwise, and in counters of registers 5 - the value of the decremented. The highest bits of the numbers are recorded in the counters-registers 1/1 and 5/1, respectively. At the outputs of the flip-flops 3 and 6/1, there are resolving potentials, and at the outputs of the flip-flops (6/2) - (b / n) prohibitory.

To perform the subtraction operations, the generator 2 generates packs of pulses. The number of pulses in the bursts at the first and fourth outputs of the generator 2 is equal to the base of the selected number system. The pulse packet at the second output of the generator 2 contains one less pulse. At the third and fifth outputs of the generator 2, one pulse is generated. A pulse at the control input of the generator 2 controls the sequence of formation of the pulse bursts.

Let us assume that the decreasing is A,. The deductible is B, and the base of the selected number system is 0. Accordingly, the state of the register counters 1 / i and 5 / i is equal to B4 and Ai.

The generator 2 pulses from the first and second output begin to flow into the input of the counter 1 / i and through the element AND 4 / i to the input of the counter-register 5 / i. Through the QB | - pulses at the output of the counter 1/1, the overfill pulse translating trigger 3 / i to prohibit state. To this point in time to the input of the counter 5 / i. Q- (Bj + l) pulses arrive through the AND 4 / i element, since in the second packet there is one less pulse than in the first one. The state of the 5 / i counter becomes equal to A + Q-l-Bi. After the end of the last pulse in the bursts from the third and fourth outputs of the generator 2, one pulse arrives, bringing the triggers 3 to the initial state, and also adding to the state of the counter-register 5 / p. In the event of the overflow of the 5 / J counter in the subtraction process, the corresponding trigger b / j is translated by the onset of the overflow pulse into the enable state, allowing the pulse to pass from the third output of the generator 2 through the And 7 / j element to the input of the counter register 5 / J-1. By its termination, this impulse translates the triggers 3 and b into the initial state, preparing the device for a new subtraction. B. In the case of A B, an overflow pulse from the output of the 5/1 counter-register translates the 6/1 trigger into a single state, and the signal from its zero output prevents the pulse from passing through the AND 7/1 element to the control input of the generator 2. Subtraction process for this case ends at this stage.

In case A; An overflow pulse from the output of the counter-register 5/1 does not occur. The trigger 6/1 is reset in a state that permits the passage of a pulse from the third output of generator 2 through the element 7/1 to the control input of generator 2. This pulse carries information that the resulting difference (A-b) has a negative value.

Claims (1)

The subtraction process continues with the formation of pulses at the first and fourth outputs of the generator 2 arriving at the inputs of counters-registers 1 at the inputs of the element AND 8 and at the third inputs of the counters-registers 5. Overflow pulse from output 5 of the i-oro counter-register 5 through the i element And .8 arrives at the installation input of the i-th counter-register 1, transferring it to the zero state. After the end of the pulse bursts, the state of the registers 5 will be overwritten, respectively, into register-registers 1. Next, pulses are formed on the third and fifth outputs of generator 2, set triggers 3 and 6 to initial conditions, and registers 5 to zero. The next step is to subtract the contents of the register 1 counters from the zero contents of the counter-registers 5 in the same way as in case A. B. This device allows the subtraction of two N-digits. If the known device allows the operation to perform a calculation. tani only for the case when the decrease is greater or. equal to the deductible, this device calculates the difference of numbers and in the case when the decrease is less than the deductible with the definition of the sign of the difference obtained. This feature of the proposed device to a greater extent meets the requirements of digital devices and control systems. Claims of Invention A device for calculating the difference of two n-bit numbers by auth.St. No. 739532, from l with the fact that, in order to expand the field of application of the device, it contains the third group of elements AND, the first input of the i-th element AND the third group is connected to the output of the corresponding counter-register decremented, and the second input - to the fourth OUTPUT of the pulse generator and the input of the corresponding counter-register of the reduced, the fifth output of the pulse generator is connected to the installation inputs of the registers of the register to be reduced, and the control inputs -. The main input is with the OUTPUT of the first element AND the second group. Sources of information taken into account in the examination 1. USSR author's certificate W 739532, cl. G About F 7/50, 1977 (prototype).