SU1051556A1 - Device for reducing information redundancy - Google Patents

Description

The invention relates to automation and all | 0 {adherent, associated with the processing and transmission of information, and can be used in various areas of industry that require reducing the amount of information stored, reducing the amount of memory required for storing information zi A device for processing and compressing and forming, containing control, scaling, and comparing units, counters, adder, and groups of elements, is known. And C 1 The disadvantages of this device are its complexity and insufficiently high speed. The closest in technical essence to the present invention is a device for reducing the redundancy of information containing the first and second arithmetic blocks {performed on comparison elements and counters), the first inputs of which are connected to the inputs of the device, the first outputs are given to the inputs of the output block, the error block and the correction unit, the inputs of which are connected to the inputs of the device, the outputs are connected to the second inputs of the first and second arithmetic, respectively, U10KOB, to the third inputs of which are connected the output the error location, the second outputs of the first and second arithmetic blocks are connected respectively to the first and second inputs of the error block and to the corresponding inputs of the output block 123 The disadvantages of this device are also its complexity and insufficiently fast performance, which makes it difficult to process signals with varying dynamics of changing information . The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that, in a device for reducing redundancy of information containing counters, the output of the first counter is connected to the summing input of the adder and the first input of the output block, the output of the second counter is connected to the subtractive input of the summator and the second input of the output block whose output is the output of the device , the elements AND, the element NOT, the OR element and the delay elements, the output of the first element AND, are connected to the first input of the first counter, and the first control input of the adder, the output of the second element. The input AND is connected to the first input of the second counter and the second control input of the adder, the inverse sign I output of which is connected to the first input I of the first element AND, the direct sign output of the adder is connected to: the first input of the OR element and the first input of the third element AND, the second the input of which is connected to the second input of the first element AND and subalution to the first input of the device, the information outputs of the adder are connected through the fourth element AND to the primary input of the OR element, the output of which is connected directly to the first input of the second element And through the element NOT with the first input of the fifth element And, the second inputs of the second and fifth elements And are connected and connected to the second input of the device, the output of the third element And is connected to the third input of the output unit and through the first delay element with the second input of the first counter , the output of the fifth element I is connected to the fourth input of the output unit and through the second element - the delay with the second input of the second counter. In addition, the output block is made on the elements AND and the OR element, the output of which is connected to the first inputs of the first and second elements AND, the outputs of which are connected to the output of the output block, the second inputs of the first elements And, the second; e the inputs of the second elements And, the first and second the inputs of the OR input are connected respectively to the first, second, third to the fourth inputs of the output unit. FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of the output block. The device (Fig. 1} contains the first and second counters I to 2, the adder 3, the elements And 4-8, the element OR 9, the element NOT 10, the first and second elements i and 12 of the delay, the output unit 13. The output unit 13 (Fig 2) contains the element OR 14, the first and second elements AND 15 and 152 The first and second counters 1 and 2 serve to sum up the single current values of the variables coming from the elements 4 and 5 and the correction pulses from the elements 1 and 12 of the delay. The adder 3 serves to compute the error functions. The first and second control inputs of the adder are connected by with the outputs of the AND 4 and I8 elements, respectively control the selection of the arithmetic operator for subtracting the contents of counter 2 and summing the contents of counter 1. The first and second elements of AND 4 and 5 serve to generate signals at the moments of arrival at their first inputs of pulses of unit increments of variables if the contents of the adder 3, respectively, greater than or equal to zero and less than or equal to zero. The third and fifth elements AND 6 and 7 serve to generate signals at the time of arrival at their first inputs of pulses of single increments of variables x, if the contents sum Matora 3 respectively less than or greater than zero. The fourth element and 8, the inputs of which. bitwise connected to the data outputs of the adder 3, it is an indicator I zero and produces a single signal at its output if the content of the adder is zero. i Element OR 9 is used to assemble signals. The NOT 10 element is an indicator of a positive non-zero number and generates a signal at its output if the contents of adder 3 are greater than zero. The first and second delay elements 11 and 12 serve to delay the signals by the time required to read information from counters 1 and 2. Output unit 13 serves to output information about the relative coordinates of the ends of the segments in the computer at the moments of arrival on its control inputs of pulses B1 from one of the outputs of AND 6 and 7. Element OR 14 (Fig. 2) serves to assemble strobe signals that allow the output of data. The elements And 15 and And serve for the issuance of data on the relative coordinates of the rectilinear segments from counters 1 and 2, respectively. The device processes the information represented by the unitary code, i.e. in the form of unitary elementary increments for each of the coordinates. Oktychiki 1 and 2 carry out summation and Г Г Г л. GH. And IZAY. Y. incrementing ijJ J a adder 3 performs the calculation of the error function) where LH; and aV Take the value of either O or 1, J of the initial state, the contents of the counter 1, 2 and adder 3 are equal to zero. The operation of the device is determined by the sign and value of the number of the number in the adder. If the content of the adder 3 is zero and positive, then the resolving potential and pulses arriving at the first input of the And 4 element will be fed to the input of the element AND 4 associated with the inverse output of the sign bit of the adder 3, adding a single increment to its content, and to the first control input of adder 3, allowing subtraction from the contents of adder 3, the contents of counter 2- This process is repeated with the arrival of each pulse until the contents of adder 3 become negative and element 4 will close. If the content of the adder is zero or negative, then the input potential of the element 5 through the CHI element 9 from the output of the element 8 and the direct sign output of the adder 3 will be allowed to resolve, so the pulses arriving at the first input of the element 5 will go to the input of counter 2 is added to its contents by a single increment, and to the second control input of adder 3, allowing the summation of the contents of counter 1 to the contents of adder 3. This process is repeated with the arrival of each pulse for as long as. the contents of the adder 3 will not be greater than zero and the element AND 5 will close. If the contents of the adder 3 is less or greater than zero, then the resolving potentials will be present at the second inputs of elements 6 and 7, respectively, and if a pulse appears on the first input of these elements, it will pass to the output of the element and to the control input of the block 13, allowing the issuance of the contents of counters 1 and 2 to the trunk. After this, the counters 1, 2 and the adder 3 are zeroed and, depending on which element the signal came from (element 6 or 7) at the input of the corresponding counter 1 or 2, the signal will come from the output of one of the elements 11 or 12 delay by adding a single increment to the contents of the counter and the device can again process the increments arriving at its inputs. The principle of operation of the device is illustrated by the example of processing a real trajectory, placed in a table, where the states of the elements of the device are shown during its operation &

Oh oh

one

about

one

Have

about

2

-3

oh oh

oh oh

one

2

3 3 4 5 5 О О

1 3; 5

The arrival of each increment to the input of the prototype device is accompanied by the following operations: transferring the contents of one of the counters to the error block one clock and performing a logical condition — one clock. The processing of one increment may require three cycles. The proposed device is of the predictive type. Data is issued in. it at the time of the arrival of the next increment, i.e. without additional time and one cycle is required to correct the contents of the counters. Thus, the speed of the proposed device exceeds the device prototype at least / RI times. The proposed device works according to the principle of prediction and with the arrival of each successive increment it immediately becomes known whether this increment belongs to the segment being processed or not, therefore the device has high speed and allows to process information as it arrives, i.e. in real time. The proposed device is structurally simpler than the base prototype object and can process information at speeds inaccessible to the base case.

1

j ..

.J lliLlj L

L.

one

0t / 8.2

Claims (2)

(57) 1. A DEVICE FOR REDUCING INFORMATION REDUNDANCE, containing counters, the output of the first counter is connected to the summing input of the adder and the first input of the output unit, the output of the second counter is connected to the subtracting input of the adder and the second input of the output unit, the output of which is the output of the device, characterized in that, in order to improve the performance of the device, AND elements, an NOT element, an OR element and delay elements are introduced into it, the output of the first AND element is connected to the first input of the first counter and the first control in by the adder, the output of the second AND element is connected to the first input of the second counter and the second control input of the adder, whose inverse sign output is connected to the first input of the first And element, the direct sign output of the adder is connected to the first input of the OR element and the first input of the third And element, the second input which is combined with the second input of the first AND element and connected to the first input of the device, the information outputs of the adder are connected through the fourth AND element to the second input of the OR element, the output of which is not connected directly with the first input of the second element AND and through the element NOT with the first input of the fifth element Y, the second inputs of the second and fifth elements AND are combined and connected to the second input of the device, the output of the third element And is connected to the third input of the output unit and through the first delay element to the second the input of the first 9 counter, the output of the fifth element And is connected to the fourth input of the output block and through the second delay element with the second input of the second counter. 2. The device according to claim 1, characterized in that the output unit is made on the AND elements and the OR element, the output of which is connected to the first inputs of the first and second elements AND, the outputs of which are connected to the output of the output unit, the second inputs of the first elements AND, the second inputs of the second AND elements, the first and second inputs of the OR element are connected respectively to the first, second, third and fourth inputs of the output block.